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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Qualify several calls to functions in the MVT namespace, for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37230 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2722,7 +2722,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case TargetLowering::Promote: {
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MVT::ValueType OVT = Tmp1.getValueType();
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MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
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unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
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unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
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Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
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@ -2760,16 +2760,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case ISD::CTTZ:
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//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
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DAG.getConstant(getSizeInBits(NVT), NVT),
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DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
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ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
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DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
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DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
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break;
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case ISD::CTLZ:
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// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
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Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
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DAG.getConstant(getSizeInBits(NVT) -
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getSizeInBits(OVT), NVT));
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DAG.getConstant(MVT::getSizeInBits(NVT) -
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MVT::getSizeInBits(OVT), NVT));
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break;
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}
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break;
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@ -3527,7 +3527,8 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
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Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
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Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
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DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
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DAG.getConstant(MVT::getSizeInBits(NVT) -
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MVT::getSizeInBits(VT),
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TLI.getShiftAmountTy()));
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break;
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case ISD::CTPOP:
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@ -3544,15 +3545,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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case ISD::CTTZ:
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// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
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DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
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DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
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ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
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DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
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DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
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break;
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case ISD::CTLZ:
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//Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
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Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
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DAG.getConstant(getSizeInBits(NVT) -
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getSizeInBits(VT), NVT));
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DAG.getConstant(MVT::getSizeInBits(NVT) -
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MVT::getSizeInBits(VT), NVT));
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break;
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}
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break;
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@ -4639,7 +4641,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
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};
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType ShVT = TLI.getShiftAmountTy();
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unsigned len = getSizeInBits(VT);
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unsigned len = MVT::getSizeInBits(VT);
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for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
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//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
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SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
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@ -4662,7 +4664,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
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// but see also: http://www.hackersdelight.org/HDcode/nlz.cc
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType ShVT = TLI.getShiftAmountTy();
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unsigned len = getSizeInBits(VT);
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unsigned len = MVT::getSizeInBits(VT);
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for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
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SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
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Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
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@ -4684,7 +4686,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
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if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
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TLI.isOperationLegal(ISD::CTLZ, VT))
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return DAG.getNode(ISD::SUB, VT,
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DAG.getConstant(getSizeInBits(VT), VT),
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DAG.getConstant(MVT::getSizeInBits(VT), VT),
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DAG.getNode(ISD::CTLZ, VT, Tmp3));
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return DAG.getNode(ISD::CTPOP, VT, Tmp3);
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}
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@ -310,14 +310,14 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
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const VectorType *PTy = cast<VectorType>(V->getType());
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unsigned NumElts = PTy->getNumElements();
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MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
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MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
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MVT::ValueType VecTy = MVT::getVectorType(EltTy, NumElts);
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// Divide the input until we get to a supported size. This will always
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// end with a scalar if the target doesn't support vectors.
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while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
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NumElts >>= 1;
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NumVectorRegs <<= 1;
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VecTy = getVectorType(EltTy, NumElts);
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VecTy = MVT::getVectorType(EltTy, NumElts);
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}
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// Check that VecTy isn't a 1-element vector.
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@ -1689,7 +1689,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default){
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unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
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unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
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Case& FrontCase = *CR.Range.first;
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Case& BackCase = *(CR.Range.second-1);
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@ -4187,7 +4187,7 @@ static SDOperand getMemsetStringVal(MVT::ValueType VT,
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SelectionDAG &DAG, TargetLowering &TLI,
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std::string &Str, unsigned Offset) {
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uint64_t Val = 0;
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unsigned MSB = getSizeInBits(VT) / 8;
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unsigned MSB = MVT::getSizeInBits(VT) / 8;
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if (TLI.isLittleEndian())
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Offset = Offset + MSB - 1;
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for (unsigned i = 0; i != MSB; ++i) {
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@ -4241,7 +4241,7 @@ static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
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unsigned NumMemOps = 0;
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while (Size != 0) {
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unsigned VTSize = getSizeInBits(VT) / 8;
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unsigned VTSize = MVT::getSizeInBits(VT) / 8;
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while (VTSize > Size) {
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VT = (MVT::ValueType)((unsigned)VT - 1);
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VTSize >>= 1;
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@ -4280,7 +4280,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
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unsigned Offset = 0;
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for (unsigned i = 0; i < NumMemOps; i++) {
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MVT::ValueType VT = MemOps[i];
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unsigned VTSize = getSizeInBits(VT) / 8;
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unsigned VTSize = MVT::getSizeInBits(VT) / 8;
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SDOperand Value = getMemsetValue(Op2, VT, DAG);
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SDOperand Store = DAG.getStore(getRoot(), Value,
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getMemBasePlusOffset(Op1, Offset, DAG, TLI),
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@ -4321,7 +4321,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
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for (unsigned i = 0; i < NumMemOps; i++) {
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MVT::ValueType VT = MemOps[i];
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unsigned VTSize = getSizeInBits(VT) / 8;
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unsigned VTSize = MVT::getSizeInBits(VT) / 8;
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SDOperand Value, Chain, Store;
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if (CopyFromStr) {
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@ -145,7 +145,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
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else
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Op += "<null:" + itostr(M->getOffset()) + ">";
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} else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) {
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Op = Op + " VT=" + getValueTypeString(N->getVT());
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Op = Op + " VT=" + MVT::getValueTypeString(N->getVT());
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} else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) {
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Op = Op + "\"" + N->getValue() + "\"";
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} else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Node)) {
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@ -299,12 +299,12 @@ unsigned TargetLowering::getVectorTypeBreakdown(const VectorType *PTy,
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// Divide the input until we get to a supported size. This will always
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// end with a scalar if the target doesn't support vectors.
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while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
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while (NumElts > 1 && !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
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NumElts >>= 1;
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NumVectorRegs <<= 1;
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}
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MVT::ValueType VT = getVectorType(EltTy, NumElts);
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MVT::ValueType VT = MVT::getVectorType(EltTy, NumElts);
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if (!isTypeLegal(VT))
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VT = EltTy;
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PTyElementVT = VT;
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