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Add a pseudo instruction REG_SEQUENCE that takes a list of registers and

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sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-05-01 00:28:44 +00:00
parent 95140a4cc1
commit b55c8bed9d
4 changed files with 29 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
utils/TableGen/CodeEmitterGen.cpp
+6 -3
View File
@@ -35,7 +35,8 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
R->getName() == "IMPLICIT_DEF" ||
R->getName() == "SUBREG_TO_REG" ||
R->getName() == "COPY_TO_REGCLASS" ||
R->getName() == "DBG_VALUE") continue;
R->getName() == "DBG_VALUE" ||
R->getName() == "REG_SEQUENCE") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
@@ -113,7 +114,8 @@ void CodeEmitterGen::run(raw_ostream &o) {
R->getName() == "IMPLICIT_DEF" ||
R->getName() == "SUBREG_TO_REG" ||
R->getName() == "COPY_TO_REGCLASS" ||
R->getName() == "DBG_VALUE") {
R->getName() == "DBG_VALUE" ||
R->getName() == "REG_SEQUENCE") {
o << " 0U,\n";
continue;
}
@@ -152,7 +154,8 @@ void CodeEmitterGen::run(raw_ostream &o) {
InstName == "IMPLICIT_DEF" ||
InstName == "SUBREG_TO_REG" ||
InstName == "COPY_TO_REGCLASS" ||
InstName == "DBG_VALUE") continue;
InstName == "DBG_VALUE" ||
InstName == "REG_SEQUENCE") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();