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Add a pseudo instruction REG_SEQUENCE that takes a list of registers and

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sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-05-01 00:28:44 +00:00
parent 95140a4cc1
commit b55c8bed9d
4 changed files with 29 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
utils/TableGen/CodeGenTarget.cpp
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@@ -326,6 +326,7 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
const CodeGenInstruction *COPY_TO_REGCLASS =
GetInstByName("COPY_TO_REGCLASS", Insts);
const CodeGenInstruction *DBG_VALUE = GetInstByName("DBG_VALUE", Insts);
const CodeGenInstruction *REG_SEQUENCE = GetInstByName("REG_SEQUENCE", Insts);
// Print out the rest of the instructions now.
InstrsByEnum.push_back(PHI);
@@ -340,6 +341,7 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
InstrsByEnum.push_back(SUBREG_TO_REG);
InstrsByEnum.push_back(COPY_TO_REGCLASS);
InstrsByEnum.push_back(DBG_VALUE);
InstrsByEnum.push_back(REG_SEQUENCE);
unsigned EndOfPredefines = InstrsByEnum.size();
@@ -357,7 +359,8 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
CGI != IMPLICIT_DEF &&
CGI != SUBREG_TO_REG &&
CGI != COPY_TO_REGCLASS &&
CGI != DBG_VALUE)
CGI != DBG_VALUE &&
CGI != REG_SEQUENCE)
InstrsByEnum.push_back(CGI);
}