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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
Add call frame setup instruction elimination and lowerid for bunch of call-related stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70728 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -426,5 +426,6 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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default: return NULL;
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case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
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case MSP430ISD::RRA: return "MSP430ISD::RRA";
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case MSP430ISD::CALL: return "MSP430ISD::CALL";
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}
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}
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@ -25,7 +25,7 @@ using namespace llvm;
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MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
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: TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
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RI(*this), TM(tm) {}
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RI(tm, *this), TM(tm) {}
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bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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@ -22,7 +22,9 @@ class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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//===----------------------------------------------------------------------===//
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// Type Profiles.
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//===----------------------------------------------------------------------===//
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def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
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def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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@ -34,6 +36,12 @@ def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
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def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
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[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
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def MSP430callseq_start :
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SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
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[SDNPHasChain, SDNPOutFlag]>;
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def MSP430callseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Operand Definitions.
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@ -63,19 +71,48 @@ def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
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def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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// Instruction list..
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// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber SRW.
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let Defs = [SPW, SRW], Uses = [SPW] in {
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(MSP430callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
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"#ADJCALLSTACKUP",
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[(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
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}
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let neverHasSideEffects = 1 in
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def NOP : Pseudo<(outs), (ins), "nop", []>;
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//===----------------------------------------------------------------------===//
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// Real Instructions
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1 in {
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def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
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def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. SPW is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [R12W, R13W, R14W, R15W, SRW],
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Uses = [SPW] in {
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def CALL32r : Pseudo<(outs), (ins GR16:$dst, variable_ops),
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"call\t{*}$dst", [(MSP430call GR16:$dst)]>;
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def CALL32m : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
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"call\t{*}$dst", [(MSP430call (load addr:$dst))]>;
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}
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//===----------------------------------------------------------------------===//
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// Move Instructions
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@ -15,8 +15,10 @@
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#include "MSP430.h"
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#include "MSP430RegisterInfo.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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@ -24,9 +26,12 @@
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using namespace llvm;
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// FIXME: Provide proper call frame setup / destroy opcodes.
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MSP430RegisterInfo::MSP430RegisterInfo(const TargetInstrInfo &tii)
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: MSP430GenRegisterInfo(MSP430::NOP, MSP430::NOP),
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TII(tii) {}
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MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
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const TargetInstrInfo &tii)
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: MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
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TM(tm), TII(tii) {
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StackAlign = TM.getFrameInfo()->getStackAlignment();
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}
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const unsigned*
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MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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@ -73,6 +78,68 @@ bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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void MSP430RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub SPW, <amt>' and the
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// adjcallstackdown instruction into 'add SPW, <amt>'
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// TODO: consider using push / pop instead of sub + store / add
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
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MachineInstr *New = 0;
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if (Old->getOpcode() == getCallFrameSetupOpcode()) {
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::SUB16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(Amount);
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} else {
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assert(Old->getOpcode() == getCallFrameDestroyOpcode());
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// factor out the amount the callee already popped.
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uint64_t CalleeAmt = Old->getOperand(1).getImm();
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Amount -= CalleeAmt;
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if (Amount)
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::ADD16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(Amount);
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}
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if (New) {
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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} else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
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// If we are performing frame pointer elimination and if the callee pops
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// something off the stack pointer, add it back.
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if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
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MachineInstr *Old = I;
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MachineInstr *New =
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BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
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MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void
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MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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@ -20,12 +20,18 @@
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namespace llvm {
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class TargetInstrInfo;
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class MSP430TargetMachine;
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struct MSP430RegisterInfo : public MSP430GenRegisterInfo {
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private:
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MSP430TargetMachine &TM;
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const TargetInstrInfo &TII;
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/// StackAlign - Default stack alignment.
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///
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unsigned StackAlign;
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public:
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MSP430RegisterInfo(const TargetInstrInfo &tii);
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MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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@ -36,6 +42,11 @@ public:
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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