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Don't cache the instruction and register info from the TargetMachine, because

Browse Source 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2013-06-07 20:28:55 +00:00
parent ce961477be
commit b5632b5b45
21 changed files with 75 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/R600/AMDGPUIndirectAddressing.cpp
View File

@ -39,7 +39,7 @@ private:
public:
AMDGPUIndirectAddressingPass(TargetMachine &tm) :
MachineFunctionPass(ID),
TII(static_cast<const AMDGPUInstrInfo*>(tm.getInstrInfo()))
TII(0)
{ }
virtual bool runOnMachineFunction(MachineFunction &MF);
@ -59,6 +59,8 @@ FunctionPass *llvm::createAMDGPUIndirectAddressingPass(TargetMachine &tm) {
bool AMDGPUIndirectAddressingPass::runOnMachineFunction(MachineFunction &MF) {
MachineRegisterInfo &MRI = MF.getRegInfo();
TII = static_cast<const AMDGPUInstrInfo*>(MF.getTarget().getInstrInfo());
int IndirectBegin = TII->getIndirectIndexBegin(MF);
int IndirectEnd = TII->getIndirectIndexEnd(MF);

2
lib/Target/R600/AMDGPUInstrInfo.cpp
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@ -28,7 +28,7 @@
using namespace llvm;
AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
: AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { }
: AMDGPUGenInstrInfo(0,0), RI(tm), TM(tm) { }
const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
return RI;

6
lib/Target/R600/AMDGPURegisterInfo.cpp
View File

@ -17,11 +17,9 @@
using namespace llvm;
AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
const TargetInstrInfo &tii)
AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm)
: AMDGPUGenRegisterInfo(0),
TM(tm),
TII(tii)
TM(tm)
{ }
//===----------------------------------------------------------------------===//

3
lib/Target/R600/AMDGPURegisterInfo.h
View File

@ -30,10 +30,9 @@ class TargetInstrInfo;
struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
TargetMachine &TM;
const TargetInstrInfo &TII;
static const uint16_t CalleeSavedReg;
AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
AMDGPURegisterInfo(TargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const {
assert(!"Unimplemented"); return BitVector();

19
lib/Target/R600/AMDILCFGStructurizer.cpp
View File

@ -2472,23 +2472,26 @@ public:
protected:
TargetMachine &TM;
const TargetInstrInfo *TII;
const AMDGPURegisterInfo *TRI;
public:
AMDGPUCFGStructurizer(char &pid, TargetMachine &tm);
const TargetInstrInfo *getTargetInstrInfo() const;
const AMDGPURegisterInfo *getTargetRegisterInfo() const;
};
} // end anonymous namespace
AMDGPUCFGStructurizer::AMDGPUCFGStructurizer(char &pid, TargetMachine &tm)
: MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
TRI(static_cast<const AMDGPURegisterInfo *>(tm.getRegisterInfo())) {
: MachineFunctionPass(pid), TM(tm) {
}
const TargetInstrInfo *AMDGPUCFGStructurizer::getTargetInstrInfo() const {
return TII;
return TM.getInstrInfo();
}
const AMDGPURegisterInfo *AMDGPUCFGStructurizer::getTargetRegisterInfo() const {
return static_cast<const AMDGPURegisterInfo *>(TM.getRegisterInfo());
}
//===----------------------------------------------------------------------===//
//
// CFGPrepare
@ -3017,7 +3020,8 @@ FunctionPass *llvm::createAMDGPUCFGPreparationPass(TargetMachine &tm) {
}
bool AMDGPUCFGPrepare::runOnMachineFunction(MachineFunction &func) {
return CFGStructurizer<AMDGPUCFGStructurizer>().prepare(func, *this, TRI);
return CFGStructurizer<AMDGPUCFGStructurizer>().prepare(func, *this,
getTargetRegisterInfo());
}
// createAMDGPUCFGStructurizerPass- Returns a pass
@ -3026,5 +3030,6 @@ FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm) {
}
bool AMDGPUCFGPerform::runOnMachineFunction(MachineFunction &func) {
return CFGStructurizer<AMDGPUCFGStructurizer>().run(func, *this, TRI);
return CFGStructurizer<AMDGPUCFGStructurizer>().run(func, *this,
getTargetRegisterInfo());
}

16
lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@ -49,7 +49,7 @@ private:
static char ID;
const R600InstrInfo *TII;
const R600RegisterInfo &TRI;
const R600RegisterInfo *TRI;
unsigned MaxFetchInst;
const AMDGPUSubtarget &ST;
@ -122,8 +122,8 @@ private:
if (AMDGPU::R600_Reg128RegClass.contains(Reg))
DstMI = Reg;
else
DstMI = TRI.getMatchingSuperReg(Reg,
TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
DstMI = TRI->getMatchingSuperReg(Reg,
TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
&AMDGPU::R600_Reg128RegClass);
}
if (MO.isUse()) {
@ -131,8 +131,8 @@ private:
if (AMDGPU::R600_Reg128RegClass.contains(Reg))
SrcMI = Reg;
else
SrcMI = TRI.getMatchingSuperReg(Reg,
TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
SrcMI = TRI->getMatchingSuperReg(Reg,
TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
&AMDGPU::R600_Reg128RegClass);
}
}
@ -318,14 +318,16 @@ private:
public:
R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())),
TRI(TII->getRegisterInfo()),
TII (0), TRI(0),
ST(tm.getSubtarget<AMDGPUSubtarget>()) {
const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
MaxFetchInst = ST.getTexVTXClauseSize();
}
virtual bool runOnMachineFunction(MachineFunction &MF) {
TII=static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
unsigned MaxStack = 0;
unsigned CurrentStack = 0;
bool HasPush = false;

4
lib/Target/R600/R600EmitClauseMarkers.cpp
View File

@ -205,9 +205,11 @@ private:
public:
R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
TII(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;

3
lib/Target/R600/R600ExpandSpecialInstrs.cpp
View File

@ -38,7 +38,7 @@ private:
public:
R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
TII(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
@ -56,6 +56,7 @@ FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
}
bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
const R600RegisterInfo &TRI = TII->getRegisterInfo();

8
lib/Target/R600/R600ISelLowering.cpp
View File

@ -26,8 +26,7 @@
using namespace llvm;
R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
AMDGPUTargetLowering(TM),
TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
AMDGPUTargetLowering(TM) {
addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
@ -117,6 +116,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
MachineFunction * MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
MachineBasicBlock::iterator I = *MI;
const R600InstrInfo *TII =
static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
switch (MI->getOpcode()) {
default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
@ -536,6 +537,9 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
MachineSDNode *interp;
if (ijb < 0) {
const MachineFunction &MF = DAG.getMachineFunction();
const R600InstrInfo *TII =
static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
return DAG.getTargetExtractSubreg(

2
lib/Target/R600/R600ISelLowering.h
View File

@ -40,8 +40,6 @@ public:
SmallVectorImpl<SDValue> &InVals) const;
virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const;
private:
const R600InstrInfo * TII;
/// Each OpenCL kernel has nine implicit parameters that are stored in the
/// first nine dwords of a Vertex Buffer. These implicit parameters are
/// lowered to load instructions which retreive the values from the Vertex

2
lib/Target/R600/R600InstrInfo.cpp
View File

@ -30,7 +30,7 @@ using namespace llvm;
R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
: AMDGPUInstrInfo(tm),
RI(tm, *this),
RI(tm),
ST(tm.getSubtarget<AMDGPUSubtarget>())
{ }

3
lib/Target/R600/R600OptimizeVectorRegisters.cpp
View File

@ -104,7 +104,7 @@ private:
public:
static char ID;
R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
TII(0) { }
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
@ -314,6 +314,7 @@ void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
}
bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
TII = static_cast<const R600InstrInfo *>(Fn.getTarget().getInstrInfo());
MRI = &(Fn.getRegInfo());
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {

11
lib/Target/R600/R600RegisterInfo.cpp
View File

@ -20,11 +20,9 @@
using namespace llvm;
R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
const TargetInstrInfo &tii)
: AMDGPURegisterInfo(tm, tii),
TM(tm),
TII(tii)
R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm)
: AMDGPURegisterInfo(tm),
TM(tm)
{ RCW.RegWeight = 0; RCW.WeightLimit = 0;}
BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
@ -55,7 +53,8 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(*I);
}
const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII);
const R600InstrInfo *RII =
static_cast<const R600InstrInfo*>(TM.getInstrInfo());
std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF);
for (std::vector<unsigned>::iterator I = IndirectRegs.begin(),
E = IndirectRegs.end();

4
lib/Target/R600/R600RegisterInfo.h
View File

@ -21,14 +21,12 @@
namespace llvm {
class R600TargetMachine;
class TargetInstrInfo;
struct R600RegisterInfo : public AMDGPURegisterInfo {
AMDGPUTargetMachine &TM;
const TargetInstrInfo &TII;
RegClassWeight RCW;
R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
R600RegisterInfo(AMDGPUTargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const;

13
lib/Target/R600/SIISelLowering.cpp
View File

@ -30,9 +30,7 @@ const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
using namespace llvm;
SITargetLowering::SITargetLowering(TargetMachine &TM) :
AMDGPUTargetLowering(TM),
TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
TRI(TM.getRegisterInfo()) {
AMDGPUTargetLowering(TM) {
addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
@ -257,6 +255,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
case AMDGPU::BRANCH: return BB;
case AMDGPU::SI_ADDR64_RSRC: {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
unsigned SuperReg = MI->getOperand(0).getReg();
unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
@ -582,6 +582,8 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
bool &ScalarSlotUsed) const {
MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
return false;
@ -621,7 +623,10 @@ bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
SDNode *Node = Op.getNode();
const TargetRegisterClass *OpClass;
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
if (OpClassID == -1) {
@ -697,6 +702,8 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
// Original encoding (either e32 or e64)
int Opcode = Node->getMachineOpcode();
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
const MCInstrDesc *Desc = &TII->get(Opcode);
unsigned NumDefs = Desc->getNumDefs();

3
lib/Target/R600/SIISelLowering.h
View File

@ -21,9 +21,6 @@
namespace llvm {
class SITargetLowering : public AMDGPUTargetLowering {
const SIInstrInfo * TII;
const TargetRegisterInfo * TRI;
SDValue LowerParameter(SelectionDAG &DAG, EVT VT, SDLoc DL,
SDValue Chain, unsigned Offset) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;

16
lib/Target/R600/SIInsertWaits.cpp
View File

@ -47,7 +47,7 @@ class SIInsertWaits : public MachineFunctionPass {
private:
static char ID;
const SIInstrInfo *TII;
const SIRegisterInfo &TRI;
const SIRegisterInfo *TRI;
const MachineRegisterInfo *MRI;
/// \brief Constant hardware limits
@ -97,8 +97,8 @@ private:
public:
SIInsertWaits(TargetMachine &tm) :
MachineFunctionPass(ID),
TII(static_cast<const SIInstrInfo*>(tm.getInstrInfo())),
TRI(TII->getRegisterInfo()) { }
TII(0),
TRI(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
@ -137,7 +137,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
assert(Op.isReg() && "First LGKM operand must be a register!");
unsigned Reg = Op.getReg();
unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
Result.Named.LGKM = Size > 4 ? 2 : 1;
} else {
@ -182,12 +182,12 @@ RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) {
return std::make_pair(0, 0);
unsigned Reg = Op.getReg();
unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
assert(Size >= 4);
RegInterval Result;
Result.first = TRI.getEncodingValue(Reg);
Result.first = TRI->getEncodingValue(Reg);
Result.second = Result.first + Size / 4;
return Result;
@ -328,9 +328,11 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
}
bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
bool Changes = false;
TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
MRI = &MF.getRegInfo();
WaitedOn = ZeroCounts;

2
lib/Target/R600/SIInstrInfo.cpp
View File

@ -24,7 +24,7 @@ using namespace llvm;
SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
: AMDGPUInstrInfo(tm),
RI(tm, *this)
RI(tm)
{ }
const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {

5
lib/Target/R600/SILowerControlFlow.cpp
View File

@ -91,8 +91,7 @@ private:
public:
SILowerControlFlowPass(TargetMachine &tm) :
MachineFunctionPass(ID), TRI(tm.getRegisterInfo()),
TII(tm.getInstrInfo()) { }
MachineFunctionPass(ID), TRI(0), TII(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
@ -408,6 +407,8 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
}
bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getTarget().getInstrInfo();
TRI = MF.getTarget().getRegisterInfo();
bool HaveKill = false;
bool NeedWQM = false;

8
lib/Target/R600/SIRegisterInfo.cpp
View File

@ -18,11 +18,9 @@
using namespace llvm;
SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm,
const TargetInstrInfo &tii)
: AMDGPURegisterInfo(tm, tii),
TM(tm),
TII(tii)
SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
: AMDGPURegisterInfo(tm),
TM(tm)
{ }
BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

4
lib/Target/R600/SIRegisterInfo.h
View File

@ -21,13 +21,11 @@
namespace llvm {
class AMDGPUTargetMachine;
class TargetInstrInfo;
struct SIRegisterInfo : public AMDGPURegisterInfo {
AMDGPUTargetMachine &TM;
const TargetInstrInfo &TII;
SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
SIRegisterInfo(AMDGPUTargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const;