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Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-11-15 19:55:00 +00:00
parent 1de0bd1945
commit b589be9334
3 changed files with 72 additions and 8 deletions
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70
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -179,8 +179,6 @@ static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
@ -251,6 +249,11 @@ static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder);
@ -1921,12 +1924,6 @@ DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
}
static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(64 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
@ -4085,3 +4082,60 @@ static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
return S;
}
static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
unsigned imm = fieldFromInstruction32(Insn, 16, 6);
unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
DecodeStatus S = MCDisassembler::Success;
// VMOVv2f32 is ambiguous with these decodings.
if (!(imm & 0x38 && cmode == 0xF)) {
Inst.setOpcode(ARM::VMOVv2f32);
return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
}
if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(64 - imm));
return S;
}
static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
unsigned imm = fieldFromInstruction32(Insn, 16, 6);
unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
DecodeStatus S = MCDisassembler::Success;
// VMOVv4f32 is ambiguous with these decodings.
if (!(imm & 0x38) && cmode == 0xF) {
Inst.setOpcode(ARM::VMOVv4f32);
return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
}
if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(64 - imm));
return S;
}