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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22849 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-08-18 00:21:41 +00:00
parent b454cfd453
commit b5a0668d43
1 changed files with 29 additions and 0 deletions
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29
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -281,6 +281,35 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
Select(N->getOperand(1)));
break;
}
case ISD::MUL: {
unsigned Imm, Opc;
if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI,
Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
break;
}
switch (N->getValueType(0)) {
default: assert(0 && "Unhandled multiply type!");
case MVT::i32: Opc = PPC::MULLW; break;
case MVT::f32: Opc = PPC::FMULS; break;
case MVT::f64: Opc = PPC::FMUL; break;
}
CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)),
Select(N->getOperand(1)));
break;
}
case ISD::MULHS: {
assert(N->getValueType(0) == MVT::i32);
CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHW,
Select(N->getOperand(0)), Select(N->getOperand(1)));
break;
}
case ISD::MULHU: {
assert(N->getValueType(0) == MVT::i32);
CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHWU,
Select(N->getOperand(0)), Select(N->getOperand(1)));
break;
}
case ISD::FNEG: {
SDOperand Val = Select(N->getOperand(0));
MVT::ValueType Ty = N->getValueType(0);