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Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-06-06 10:14:55 +00:00
parent f94ab6a662
commit b5c1c9c8e3
3 changed files with 3 additions and 0 deletions
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utils/TableGen/CodeGenTarget.cpp
+1
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@@ -360,6 +360,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
hasCtrlDep = R->getValueAsBit("hasCtrlDep");
noResults = R->getValueAsBit("noResults");
clobbersPred = R->getValueAsBit("clobbersPred");
hasVariableNumberOfOperands = false;
DagInit *DI;