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treat TAILCALL nodes identically to CALL nodes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21977 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-05-13 20:29:26 +00:00
parent 2e7714ad2b
commit b5d8e6ece6
4 changed files with 14 additions and 4 deletions
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6
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -1193,7 +1193,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;
if (N.getOpcode() != ISD::CALL)
if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
Reg = Result = (N.getValueType() != MVT::Other) ?
MakeReg(N.getValueType()) : notIn;
else {
@ -1217,7 +1217,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
(N.getValue(0).getValueType() == MVT::f32 ||
N.getValue(0).getValueType() == MVT::f64)
))
&& opcode != ISD::CALL
&& opcode != ISD::CALL && opcode != ISD::TAILCALL
)
return SelectExprFP(N, Result);
@ -1376,6 +1376,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
.addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal());
return Result;
case ISD::TAILCALL:
case ISD::CALL:
{
Select(N.getOperand(0));
@ -2242,6 +2243,7 @@ void ISel::Select(SDOperand N) {
case ISD::ZEXTLOAD:
case ISD::LOAD:
case ISD::CopyFromReg:
case ISD::TAILCALL:
case ISD::CALL:
case ISD::DYNAMIC_STACKALLOC:
ExprMap.erase(N);

4
lib/Target/IA64/IA64ISelPattern.cpp
View File

@ -953,7 +953,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;
if (N.getOpcode() != ISD::CALL)
if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
Reg = Result = (N.getValueType() != MVT::Other) ?
MakeReg(N.getValueType()) : 1;
else {
@ -2072,6 +2072,7 @@ pC = pA OR pB
return Result;
}
case ISD::TAILCALL:
case ISD::CALL: {
Select(N.getOperand(0));
@ -2342,6 +2343,7 @@ void ISel::Select(SDOperand N) {
case ISD::ZEXTLOAD:
case ISD::SEXTLOAD:
case ISD::LOAD:
case ISD::TAILCALL:
case ISD::CALL:
case ISD::CopyFromReg:
case ISD::DYNAMIC_STACKALLOC:

3
lib/Target/PowerPC/PPC64ISelPattern.cpp
View File

@ -939,6 +939,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
Reg = Result = (N.getValueType() != MVT::Other) ?
MakeReg(N.getValueType()) : 1;
break;
case ISD::TAILCALL:
case ISD::CALL:
// If this is a call instruction, make sure to prepare ALL of the result
// values as well as the chain.
@ -1070,6 +1071,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
return Result;
}
case ISD::TAILCALL:
case ISD::CALL: {
unsigned GPR_idx = 0, FPR_idx = 0;
static const unsigned GPR[] = {
@ -1617,6 +1619,7 @@ void ISel::Select(SDOperand N) {
case ISD::ZEXTLOAD:
case ISD::LOAD:
case ISD::CopyFromReg:
case ISD::TAILCALL:
case ISD::CALL:
case ISD::DYNAMIC_STACKALLOC:
ExprMap.erase(N);

5
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -1539,6 +1539,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
Reg = Result = (N.getValueType() != MVT::Other) ?
MakeReg(N.getValueType()) : 1;
break;
case ISD::TAILCALL:
case ISD::CALL:
// If this is a call instruction, make sure to prepare ALL of the result
// values as well as the chain.
@ -1569,7 +1570,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
if (DestType == MVT::f64 || DestType == MVT::f32)
if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
ISD::UNDEF != opcode && ISD::CALL != opcode)
ISD::UNDEF != opcode && ISD::CALL != opcode && ISD::TAILCALL != opcode)
return SelectExprFP(N, Result);
switch (opcode) {
@ -1680,6 +1681,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
return Result;
}
case ISD::TAILCALL:
case ISD::CALL: {
unsigned GPR_idx = 0, FPR_idx = 0;
static const unsigned GPR[] = {
@ -2504,6 +2506,7 @@ void ISel::Select(SDOperand N) {
case ISD::ZEXTLOAD:
case ISD::LOAD:
case ISD::CopyFromReg:
case ISD::TAILCALL:
case ISD::CALL:
case ISD::DYNAMIC_STACKALLOC:
ExprMap.erase(N);