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https://github.com/c64scene-ar/llvm-6502.git
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Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
5cc16a9d89
commit
b5e1d5b46f
@ -2921,20 +2921,8 @@ let isCommutable = 0 in
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/// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
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/// classes below
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multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SizeItins itins,
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bit Is2Addr = 1> {
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defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
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OpNode, FR32, f32mem,
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itins.s, Is2Addr>, XS;
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defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
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OpNode, FR64, f64mem,
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itins.d, Is2Addr>, XD;
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}
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multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
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SDNode OpNode, SizeItins itins> {
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let Predicates = [HasAVX] in {
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defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
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VR128, v4f32, f128mem, memopv4f32,
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SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
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@ -2948,93 +2936,78 @@ let Predicates = [HasAVX] in {
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defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
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OpNode, VR256, v4f64, f256mem, memopv4f64,
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SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
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v4f32, f128mem, memopv4f32, SSEPackedSingle,
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itins.s>, TB;
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defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
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v2f64, f128mem, memopv2f64, SSEPackedDouble,
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itins.d>, TB, OpSize;
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}
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
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v4f32, f128mem, memopv4f32, SSEPackedSingle,
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itins.s, 1>, TB;
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defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
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v2f64, f128mem, memopv2f64, SSEPackedDouble,
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itins.d, 1>, TB, OpSize;
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}
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multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SizeItins itins> {
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defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
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OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
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defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
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OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
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let Constraints = "$src1 = $dst" in {
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defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
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OpNode, FR32, f32mem, itins.s>, XS;
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defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
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OpNode, FR64, f64mem, itins.d>, XD;
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}
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}
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multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
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SizeItins itins,
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bit Is2Addr = 1> {
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defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
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itins.s, Is2Addr>, XS;
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defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
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itins.d, Is2Addr>, XD;
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SizeItins itins> {
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defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
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itins.s, 0>, XS, VEX_4V, VEX_LIG;
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defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
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itins.d, 0>, XD, VEX_4V, VEX_LIG;
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let Constraints = "$src1 = $dst" in {
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defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
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itins.s>, XS;
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defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
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itins.d>, XD;
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}
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}
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// Binary Arithmetic instructions
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defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>;
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defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>;
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defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
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defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
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basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
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let isCommutable = 0 in {
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defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>;
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defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>;
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defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>;
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defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>;
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defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
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defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
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basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
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defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
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defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
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}
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let isCodeGenOnly = 1 in {
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defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
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defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
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}
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defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
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basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
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basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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let isCommutable = 0 in {
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defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
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basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
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basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
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basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
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basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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}
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let Constraints = "$src1 = $dst" in {
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defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
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defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
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let isCommutable = 0 in {
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defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
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defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
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defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
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defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
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}
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}
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let isCodeGenOnly = 1 in {
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defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
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VEX_4V, VEX_LIG;
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let Constraints = "$src1 = $dst" in {
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defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
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defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
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}
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defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
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defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
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}
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/// Unop Arithmetic
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