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LegalizeTypes support for atomic operation promotion.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57838 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-10-20 16:17:42 +00:00
parent 49c18cce97
commit b5f68e241f
2 changed files with 78 additions and 3 deletions
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79
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -89,13 +89,65 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::XOR:
case ISD::ADD:
case ISD::SUB:
case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
case ISD::SDIV:
case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
case ISD::UDIV:
case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
case ISD::ATOMIC_LOAD_ADD_8:
case ISD::ATOMIC_LOAD_SUB_8:
case ISD::ATOMIC_LOAD_AND_8:
case ISD::ATOMIC_LOAD_OR_8:
case ISD::ATOMIC_LOAD_XOR_8:
case ISD::ATOMIC_LOAD_NAND_8:
case ISD::ATOMIC_LOAD_MIN_8:
case ISD::ATOMIC_LOAD_MAX_8:
case ISD::ATOMIC_LOAD_UMIN_8:
case ISD::ATOMIC_LOAD_UMAX_8:
case ISD::ATOMIC_SWAP_8:
case ISD::ATOMIC_LOAD_ADD_16:
case ISD::ATOMIC_LOAD_SUB_16:
case ISD::ATOMIC_LOAD_AND_16:
case ISD::ATOMIC_LOAD_OR_16:
case ISD::ATOMIC_LOAD_XOR_16:
case ISD::ATOMIC_LOAD_NAND_16:
case ISD::ATOMIC_LOAD_MIN_16:
case ISD::ATOMIC_LOAD_MAX_16:
case ISD::ATOMIC_LOAD_UMIN_16:
case ISD::ATOMIC_LOAD_UMAX_16:
case ISD::ATOMIC_SWAP_16:
case ISD::ATOMIC_LOAD_ADD_32:
case ISD::ATOMIC_LOAD_SUB_32:
case ISD::ATOMIC_LOAD_AND_32:
case ISD::ATOMIC_LOAD_OR_32:
case ISD::ATOMIC_LOAD_XOR_32:
case ISD::ATOMIC_LOAD_NAND_32:
case ISD::ATOMIC_LOAD_MIN_32:
case ISD::ATOMIC_LOAD_MAX_32:
case ISD::ATOMIC_LOAD_UMIN_32:
case ISD::ATOMIC_LOAD_UMAX_32:
case ISD::ATOMIC_SWAP_32:
case ISD::ATOMIC_LOAD_ADD_64:
case ISD::ATOMIC_LOAD_SUB_64:
case ISD::ATOMIC_LOAD_AND_64:
case ISD::ATOMIC_LOAD_OR_64:
case ISD::ATOMIC_LOAD_XOR_64:
case ISD::ATOMIC_LOAD_NAND_64:
case ISD::ATOMIC_LOAD_MIN_64:
case ISD::ATOMIC_LOAD_MAX_64:
case ISD::ATOMIC_LOAD_UMIN_64:
case ISD::ATOMIC_LOAD_UMAX_64:
case ISD::ATOMIC_SWAP_64:
Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
case ISD::ATOMIC_CMP_SWAP_8:
case ISD::ATOMIC_CMP_SWAP_16:
case ISD::ATOMIC_CMP_SWAP_32:
case ISD::ATOMIC_CMP_SWAP_64:
Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
}
// If Result is null, the sub-method took care of registering the result.
@ -120,6 +172,27 @@ SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
}
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
SDValue Op2 = GetPromotedInteger(N->getOperand(2));
SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
Op2, N->getSrcValue(), N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
return Res;
}
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
SDValue Op2 = GetPromotedInteger(N->getOperand(2));
SDValue Op3 = GetPromotedInteger(N->getOperand(3));
SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
Op2, Op3, N->getSrcValue(), N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
return Res;
}
SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
SDValue InOp = N->getOperand(0);
MVT InVT = InOp.getValueType();

2
lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -214,6 +214,8 @@ private:
void PromoteIntegerResult(SDNode *N, unsigned ResNo);
SDValue PromoteIntRes_AssertSext(SDNode *N);
SDValue PromoteIntRes_AssertZext(SDNode *N);
SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
SDValue PromoteIntRes_Atomic2(AtomicSDNode *N);
SDValue PromoteIntRes_BIT_CONVERT(SDNode *N);
SDValue PromoteIntRes_BSWAP(SDNode *N);
SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);