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Remove the SmallVector ctor that converts from a SmallVectorImpl. This

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conversion open the door for many nasty implicit conversion issues, and
can be easily solved by initializing with (V.begin(), V.end()) when 
needed.

This patch includes many small cleanups for sdisel also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-04-28 06:44:42 +00:00
parent e49e52d856
commit b606dba13b
2 changed files with 55 additions and 55 deletions
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7
include/llvm/ADT/SmallVector.h
View File

@ -491,16 +491,11 @@ public:
operator=(RHS);
}
SmallVector(const SmallVectorImpl<T> &RHS)
: SmallVectorImpl<T>(NumTsAvailable) {
if (!RHS.empty())
operator=(RHS);
}
const SmallVector &operator=(const SmallVector &RHS) {
SmallVectorImpl<T>::operator=(RHS);
return *this;
}
};
} // End llvm namespace

65
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -146,11 +146,11 @@ namespace {
unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
: TLI(&tli), Regs(1, Reg), RegVTs(1, regvt), ValueVTs(1, valuevt) {}
RegsForValue(const TargetLowering &tli,
const SmallVectorImpl<unsigned> &regs,
const SmallVector<unsigned, 4> &regs,
MVT::ValueType regvt, MVT::ValueType valuevt)
: TLI(&tli), Regs(regs), RegVTs(1, regvt), ValueVTs(1, valuevt) {}
RegsForValue(const TargetLowering &tli,
const SmallVectorImpl<unsigned> &regs,
const SmallVector<unsigned, 4> &regs,
const SmallVector<MVT::ValueType, 4> &regvts,
const SmallVector<MVT::ValueType, 4> &valuevts)
: TLI(&tli), Regs(regs), RegVTs(regvts), ValueVTs(valuevts) {}
@ -360,16 +360,15 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
/// the correctly promoted or expanded types. Assign these registers
/// consecutive vreg numbers and return the first assigned number.
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
const Type *Ty = V->getType();
SmallVector<MVT::ValueType, 4> ValueVTs;
ComputeValueVTs(TLI, Ty, ValueVTs);
ComputeValueVTs(TLI, V->getType(), ValueVTs);
unsigned FirstReg = 0;
for (unsigned Value = 0; Value != ValueVTs.size(); ++Value) {
MVT::ValueType ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI.getNumRegisters(ValueVT);
MVT::ValueType RegisterVT = TLI.getRegisterType(ValueVT);
unsigned NumRegs = TLI.getNumRegisters(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
unsigned R = MakeReg(RegisterVT);
if (!FirstReg) FirstReg = R;
@ -1042,18 +1041,22 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
if (N.Val) return N;
const Type *VTy = V->getType();
MVT::ValueType VT = TLI.getValueType(VTy, true);
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
visit(CE->getOpcode(), *CE);
SDOperand N1 = NodeMap[V];
assert(N1.Val && "visit didn't populate the ValueMap!");
return N1;
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
MVT::ValueType VT = TLI.getValueType(VTy, true);
if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
return N = DAG.getConstant(CI->getValue(), VT);
if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
return N = DAG.getGlobalAddress(GV, VT);
} else if (isa<ConstantPointerNull>(C)) {
if (isa<ConstantPointerNull>(C))
return N = DAG.getConstant(0, TLI.getPointerTy());
} else if (isa<UndefValue>(C)) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
if (isa<UndefValue>(C)) {
if (!isa<VectorType>(VTy))
return N = DAG.getNode(ISD::UNDEF, VT);
@ -1067,13 +1070,19 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
// Create a VConstant node with generic Vector type.
MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
&Ops[0], Ops.size());
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
} else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
unsigned NumElements = PTy->getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
return N = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
visit(CE->getOpcode(), *CE);
SDOperand N1 = NodeMap[V];
assert(N1.Val && "visit didn't populate the ValueMap!");
return N1;
}
const VectorType *VecTy = cast<VectorType>(VTy);
unsigned NumElements = VecTy->getNumElements();
MVT::ValueType PVT = TLI.getValueType(VecTy->getElementType());
// Now that we know the number and type of the elements, push a
// Constant or ConstantFP node onto the ops list for each element of
@ -1093,15 +1102,11 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
}
// Create a BUILD_VECTOR node.
MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
Ops.size());
} else {
// Canonicalize all constant ints to be unsigned.
return N = DAG.getConstant(cast<ConstantInt>(C)->getValue(),VT);
}
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
// If this is a static alloca, generate it as the frameindex instead of
// computation.
if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
std::map<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
@ -1114,7 +1119,6 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
RegsForValue RFV(TLI, InReg, VTy);
SDOperand Chain = DAG.getEntryNode();
return RFV.getCopyFromRegs(DAG, Chain, NULL);
}
@ -1124,6 +1128,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
return;
}
SmallVector<SDOperand, 8> NewValues;
NewValues.push_back(getControlRoot());
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
@ -3600,7 +3605,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
MachineFunction &MF = DAG.getMachineFunction();
SmallVector<unsigned, 8> Regs;
SmallVector<unsigned, 4> Regs;
// If this is a constraint for a single physreg, or a constraint for a
// register class, find it.