mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Fix casts of float to unsigned long
Replace STDX (store 64 bit int indexed) with STFDX (store double indexed) Fix latent bug in indexed load generation Generate indexed loads and stores in many more cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15626 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
91fdc01fe1
commit
b64af918cb
@ -82,9 +82,9 @@ namespace {
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std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
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// External functions used in the Module
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Function *fmodfFn, *fmodFn, *__moddi3Fn, *__divdi3Fn, *__umoddi3Fn,
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*__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__floatdisfFn, *__floatdidfFn,
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*mallocFn, *freeFn;
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Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
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*__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
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*__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
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// MBBMap - Mapping between LLVM BB -> Machine BB
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std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
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@ -103,6 +103,7 @@ namespace {
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bool doInitialization(Module &M) {
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// Add external functions that we may call
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Type *i = Type::IntTy;
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Type *d = Type::DoubleTy;
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Type *f = Type::FloatTy;
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Type *l = Type::LongTy;
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@ -112,6 +113,8 @@ namespace {
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fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
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// double fmod(double, double);
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fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
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// int __cmpdi2(long, long);
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__cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
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// long __moddi3(long, long);
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__moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
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// long __divdi3(long, long);
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@ -121,9 +124,13 @@ namespace {
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// unsigned long __udivdi3(unsigned long, unsigned long);
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__udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
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// long __fixsfdi(float)
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__fixdfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
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__fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
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// long __fixdfdi(double)
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__fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
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// unsigned long __fixunssfdi(float)
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__fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
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// unsigned long __fixunsdfdi(double)
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__fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
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// float __floatdisf(long)
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__floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
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// double __floatdidf(long)
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@ -283,7 +290,8 @@ namespace {
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void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg,
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bool CollapseRemainder, ConstantSInt **Remainder);
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bool CollapseRemainder, ConstantSInt **Remainder,
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unsigned *PendingAddReg);
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/// emitCastOperation - Common code shared between visitCastInst and
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/// constant expression cast support.
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@ -375,18 +383,18 @@ namespace {
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unsigned makeAnotherReg(const Type *Ty) {
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assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
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"Current target doesn't have PPC reg info??");
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const PowerPCRegisterInfo *MRI =
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const PowerPCRegisterInfo *PPCRI =
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static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
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if (Ty == Type::LongTy || Ty == Type::ULongTy) {
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const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
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// Create the lower part
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const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy);
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// Create the upper part
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F->getSSARegMap()->createVirtualRegister(RC);
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// Create the upper part.
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// Create the lower part.
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return F->getSSARegMap()->createVirtualRegister(RC)-1;
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}
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// Add the mapping of regnumber => reg class to MachineFunction
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const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
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const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
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return F->getSSARegMap()->createVirtualRegister(RC);
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}
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@ -2478,12 +2486,14 @@ void ISel::visitLoadInst(LoadInst &I) {
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// otherwise, we copy the offset into another reg, and use reg+reg addressing.
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if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
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unsigned baseReg = getReg(GEPI);
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unsigned pendingAdd;
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ConstantSInt *offset;
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emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
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GEPI->op_end(), baseReg, true, &offset);
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GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
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if (Class != cLong && canUseAsImmediateForOpcode(offset, 0)) {
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if (pendingAdd == 0 && Class != cLong &&
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canUseAsImmediateForOpcode(offset, 0)) {
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if (Class == cByte && I.getType()->isSigned()) {
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unsigned TmpReg = makeAnotherReg(I.getType());
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BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
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@ -2496,7 +2506,7 @@ void ISel::visitLoadInst(LoadInst &I) {
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return;
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}
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unsigned indexReg = getReg(offset);
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unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
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if (Class == cLong) {
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unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
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@ -2505,7 +2515,7 @@ void ISel::visitLoadInst(LoadInst &I) {
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BuildMI(BB, IdxOpcode, 2, DestReg+1).addReg(indexPlus4).addReg(baseReg);
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} else if (Class == cByte && I.getType()->isSigned()) {
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unsigned TmpReg = makeAnotherReg(I.getType());
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BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
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BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
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BuildMI(BB, PPC32::EXTSB, 1, DestReg).addReg(TmpReg);
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} else {
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BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
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@ -2540,7 +2550,7 @@ void ISel::visitStoreInst(StoreInst &I) {
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// Indexed opcodes, for reg+reg addressing
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static const unsigned IdxOpcodes[] = {
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PPC32::STBX, PPC32::STHX, PPC32::STWX,
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PPC32::STFSX, PPC32::STDX, PPC32::STWX
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PPC32::STFSX, PPC32::STFDX, PPC32::STWX
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};
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Value *SourceAddr = I.getOperand(1);
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@ -2558,18 +2568,20 @@ void ISel::visitStoreInst(StoreInst &I) {
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// otherwise, we copy the offset into another reg, and use reg+reg addressing.
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if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
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unsigned baseReg = getReg(GEPI);
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unsigned pendingAdd;
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ConstantSInt *offset;
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emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
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GEPI->op_end(), baseReg, true, &offset);
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GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
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if (Class != cLong && canUseAsImmediateForOpcode(offset, 0)) {
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if (0 == pendingAdd && Class != cLong &&
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canUseAsImmediateForOpcode(offset, 0)) {
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BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
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.addReg(baseReg);
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return;
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}
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unsigned indexReg = getReg(offset);
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unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
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if (Class == cLong) {
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unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
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@ -2749,11 +2761,15 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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// Handle casts from floating point to integer now...
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if (SrcClass == cFP32 || SrcClass == cFP64) {
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static Function* const Funcs[] =
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{ __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
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// emit library call
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if (DestClass == cLong) {
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bool isDouble = SrcClass == cFP64;
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unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
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std::vector<ValueRecord> Args;
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Args.push_back(ValueRecord(SrcReg, SrcTy));
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Function *floatFn = (DestClass == cFP32) ? __fixsfdiFn : __fixdfdiFn;
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Function *floatFn = Funcs[nameIndex];
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MachineInstr *TheCall =
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BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(floatFn, true);
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doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
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@ -3120,7 +3136,7 @@ void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
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unsigned outputReg = getReg(I);
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emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
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outputReg, false, 0);
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outputReg, false, 0, 0);
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}
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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@ -3130,7 +3146,8 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg,
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bool GEPIsFolded, ConstantSInt **RemainderPtr) {
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bool GEPIsFolded, ConstantSInt **RemainderPtr,
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unsigned *PendingAddReg) {
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const TargetData &TD = TM.getTargetData();
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const Type *Ty = Src->getType();
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unsigned basePtrReg = getReg(Src, MBB, IP);
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@ -3199,18 +3216,32 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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}
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}
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// Emit instructions for all the collapsed ops
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bool pendingAdd = false;
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unsigned pendingAddReg = 0;
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for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
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cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
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CollapsedGepOp& cgo = *cgo_i;
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unsigned nextBasePtrReg = makeAnotherReg (Type::IntTy);
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unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
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// If we didn't emit an add last time through the loop, we need to now so
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// that the base reg is updated appropriately.
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if (pendingAdd) {
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assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
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BuildMI(*MBB, IP, PPC32::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
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.addReg(pendingAddReg);
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basePtrReg = nextBasePtrReg;
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nextBasePtrReg = makeAnotherReg(Type::IntTy);
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pendingAddReg = 0;
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pendingAdd = false;
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}
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if (cgo.isMul) {
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// We know the elementSize is a constant, so we can emit a constant mul
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// and then add it to the current base reg
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unsigned TmpReg = makeAnotherReg(Type::IntTy);
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doMultiplyConst(MBB, IP, TmpReg, cgo.index, cgo.size);
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BuildMI(*MBB, IP, PPC32::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
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.addReg(TmpReg);
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doMultiplyConst(MBB, IP, nextBasePtrReg, cgo.index, cgo.size);
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pendingAddReg = basePtrReg;
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pendingAdd = true;
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} else {
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// Try and generate an immediate addition if possible
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if (cgo.size->isNullValue()) {
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@ -3235,16 +3266,41 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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// the target, and save the current constant offset so the folding load or
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// store can try and use it as an immediate.
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if (GEPIsFolded) {
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BuildMI (BB, PPC32::OR, 2, TargetReg).addReg(basePtrReg).addReg(basePtrReg);
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// If this is a folded GEP and the last element was an index, then we need
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// to do some extra work to turn a shift/add/stw into a shift/stwx
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if (pendingAdd && 0 == remainder->getValue()) {
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assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
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*PendingAddReg = pendingAddReg;
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} else {
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*PendingAddReg = 0;
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if (pendingAdd) {
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unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
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assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
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BuildMI(*MBB, IP, PPC32::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
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.addReg(pendingAddReg);
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basePtrReg = nextBasePtrReg;
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}
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}
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BuildMI (*MBB, IP, PPC32::OR, 2, TargetReg).addReg(basePtrReg)
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.addReg(basePtrReg);
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*RemainderPtr = remainder;
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return;
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}
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// If we still have a pending add at this point, emit it now
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if (pendingAdd) {
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unsigned TmpReg = makeAnotherReg(Type::IntTy);
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BuildMI(*MBB, IP, PPC32::ADD, 2, TmpReg).addReg(pendingAddReg)
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.addReg(basePtrReg);
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basePtrReg = TmpReg;
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}
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// After we have processed all the indices, the result is left in
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// basePtrReg. Move it to the register where we were expected to
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// put the answer.
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if (remainder->isNullValue()) {
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BuildMI (BB, PPC32::OR, 2, TargetReg).addReg(basePtrReg).addReg(basePtrReg);
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BuildMI (*MBB, IP, PPC32::OR, 2, TargetReg).addReg(basePtrReg)
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.addReg(basePtrReg);
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} else if (canUseAsImmediateForOpcode(remainder, 0)) {
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BuildMI(*MBB, IP, PPC32::ADDI, 2, TargetReg).addReg(basePtrReg)
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.addSImm(remainder->getValue());
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@ -143,10 +143,10 @@ def STW : DForm_3<"stw", 36, 0, 0>;
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def STWU : DForm_3<"stwu", 37, 0, 0>;
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def STWX : XForm_8<"stwx", 31, 151, 0, 0>;
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def STWUX : XForm_8<"stwux", 31, 183, 0, 0>;
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def STDX : XForm_8<"stdx", 31, 149, 1, 0>;
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def STFS : DForm_9<"stfs", 52, 0, 0>;
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def STFSX : XForm_28<"stfsx", 31, 302, 0, 0>;
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def STFSX : XForm_28<"stfsx", 31, 663, 0, 0>;
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def STFD : DForm_9<"stfd", 54, 0, 0>;
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def STFDX : XForm_28<"stfdx", 31, 727, 0, 0>;
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def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
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def SUB : XOForm_1_rev<"sub", 31, 40, 0, 0, 0, 0>;
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def SUBF : XOForm_1<"subf", 31, 40, 0, 0, 0, 0>;
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@ -82,9 +82,9 @@ namespace {
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std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
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// External functions used in the Module
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Function *fmodfFn, *fmodFn, *__moddi3Fn, *__divdi3Fn, *__umoddi3Fn,
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*__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__floatdisfFn, *__floatdidfFn,
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*mallocFn, *freeFn;
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Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
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*__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
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*__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
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// MBBMap - Mapping between LLVM BB -> Machine BB
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std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
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@ -103,6 +103,7 @@ namespace {
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bool doInitialization(Module &M) {
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// Add external functions that we may call
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Type *i = Type::IntTy;
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Type *d = Type::DoubleTy;
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Type *f = Type::FloatTy;
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Type *l = Type::LongTy;
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@ -112,6 +113,8 @@ namespace {
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fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
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// double fmod(double, double);
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fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
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// int __cmpdi2(long, long);
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__cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
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// long __moddi3(long, long);
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__moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
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// long __divdi3(long, long);
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@ -121,9 +124,13 @@ namespace {
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// unsigned long __udivdi3(unsigned long, unsigned long);
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__udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
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// long __fixsfdi(float)
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__fixdfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
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__fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
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// long __fixdfdi(double)
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__fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
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// unsigned long __fixunssfdi(float)
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__fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
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// unsigned long __fixunsdfdi(double)
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__fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
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// float __floatdisf(long)
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__floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
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// double __floatdidf(long)
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@ -283,7 +290,8 @@ namespace {
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void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg,
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bool CollapseRemainder, ConstantSInt **Remainder);
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bool CollapseRemainder, ConstantSInt **Remainder,
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unsigned *PendingAddReg);
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/// emitCastOperation - Common code shared between visitCastInst and
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/// constant expression cast support.
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@ -375,18 +383,18 @@ namespace {
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unsigned makeAnotherReg(const Type *Ty) {
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assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
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"Current target doesn't have PPC reg info??");
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const PowerPCRegisterInfo *MRI =
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const PowerPCRegisterInfo *PPCRI =
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static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
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if (Ty == Type::LongTy || Ty == Type::ULongTy) {
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const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
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// Create the lower part
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const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy);
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// Create the upper part
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F->getSSARegMap()->createVirtualRegister(RC);
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// Create the upper part.
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// Create the lower part.
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return F->getSSARegMap()->createVirtualRegister(RC)-1;
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||||
}
|
||||
|
||||
// Add the mapping of regnumber => reg class to MachineFunction
|
||||
const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
|
||||
const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
|
||||
return F->getSSARegMap()->createVirtualRegister(RC);
|
||||
}
|
||||
|
||||
@ -2478,12 +2486,14 @@ void ISel::visitLoadInst(LoadInst &I) {
|
||||
// otherwise, we copy the offset into another reg, and use reg+reg addressing.
|
||||
if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
|
||||
unsigned baseReg = getReg(GEPI);
|
||||
unsigned pendingAdd;
|
||||
ConstantSInt *offset;
|
||||
|
||||
emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
|
||||
GEPI->op_end(), baseReg, true, &offset);
|
||||
GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
|
||||
|
||||
if (Class != cLong && canUseAsImmediateForOpcode(offset, 0)) {
|
||||
if (pendingAdd == 0 && Class != cLong &&
|
||||
canUseAsImmediateForOpcode(offset, 0)) {
|
||||
if (Class == cByte && I.getType()->isSigned()) {
|
||||
unsigned TmpReg = makeAnotherReg(I.getType());
|
||||
BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
|
||||
@ -2496,7 +2506,7 @@ void ISel::visitLoadInst(LoadInst &I) {
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned indexReg = getReg(offset);
|
||||
unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
|
||||
|
||||
if (Class == cLong) {
|
||||
unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
|
||||
@ -2505,7 +2515,7 @@ void ISel::visitLoadInst(LoadInst &I) {
|
||||
BuildMI(BB, IdxOpcode, 2, DestReg+1).addReg(indexPlus4).addReg(baseReg);
|
||||
} else if (Class == cByte && I.getType()->isSigned()) {
|
||||
unsigned TmpReg = makeAnotherReg(I.getType());
|
||||
BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
|
||||
BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
|
||||
BuildMI(BB, PPC32::EXTSB, 1, DestReg).addReg(TmpReg);
|
||||
} else {
|
||||
BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
|
||||
@ -2540,7 +2550,7 @@ void ISel::visitStoreInst(StoreInst &I) {
|
||||
// Indexed opcodes, for reg+reg addressing
|
||||
static const unsigned IdxOpcodes[] = {
|
||||
PPC32::STBX, PPC32::STHX, PPC32::STWX,
|
||||
PPC32::STFSX, PPC32::STDX, PPC32::STWX
|
||||
PPC32::STFSX, PPC32::STFDX, PPC32::STWX
|
||||
};
|
||||
|
||||
Value *SourceAddr = I.getOperand(1);
|
||||
@ -2558,18 +2568,20 @@ void ISel::visitStoreInst(StoreInst &I) {
|
||||
// otherwise, we copy the offset into another reg, and use reg+reg addressing.
|
||||
if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
|
||||
unsigned baseReg = getReg(GEPI);
|
||||
unsigned pendingAdd;
|
||||
ConstantSInt *offset;
|
||||
|
||||
emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
|
||||
GEPI->op_end(), baseReg, true, &offset);
|
||||
GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
|
||||
|
||||
if (Class != cLong && canUseAsImmediateForOpcode(offset, 0)) {
|
||||
if (0 == pendingAdd && Class != cLong &&
|
||||
canUseAsImmediateForOpcode(offset, 0)) {
|
||||
BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
|
||||
.addReg(baseReg);
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned indexReg = getReg(offset);
|
||||
unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
|
||||
|
||||
if (Class == cLong) {
|
||||
unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
|
||||
@ -2749,11 +2761,15 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
|
||||
|
||||
// Handle casts from floating point to integer now...
|
||||
if (SrcClass == cFP32 || SrcClass == cFP64) {
|
||||
static Function* const Funcs[] =
|
||||
{ __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
|
||||
// emit library call
|
||||
if (DestClass == cLong) {
|
||||
bool isDouble = SrcClass == cFP64;
|
||||
unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
|
||||
std::vector<ValueRecord> Args;
|
||||
Args.push_back(ValueRecord(SrcReg, SrcTy));
|
||||
Function *floatFn = (DestClass == cFP32) ? __fixsfdiFn : __fixdfdiFn;
|
||||
Function *floatFn = Funcs[nameIndex];
|
||||
MachineInstr *TheCall =
|
||||
BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(floatFn, true);
|
||||
doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
|
||||
@ -3120,7 +3136,7 @@ void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
|
||||
|
||||
unsigned outputReg = getReg(I);
|
||||
emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
|
||||
outputReg, false, 0);
|
||||
outputReg, false, 0, 0);
|
||||
}
|
||||
|
||||
/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
|
||||
@ -3130,7 +3146,8 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator IP,
|
||||
Value *Src, User::op_iterator IdxBegin,
|
||||
User::op_iterator IdxEnd, unsigned TargetReg,
|
||||
bool GEPIsFolded, ConstantSInt **RemainderPtr) {
|
||||
bool GEPIsFolded, ConstantSInt **RemainderPtr,
|
||||
unsigned *PendingAddReg) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
const Type *Ty = Src->getType();
|
||||
unsigned basePtrReg = getReg(Src, MBB, IP);
|
||||
@ -3199,18 +3216,32 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
}
|
||||
}
|
||||
// Emit instructions for all the collapsed ops
|
||||
bool pendingAdd = false;
|
||||
unsigned pendingAddReg = 0;
|
||||
|
||||
for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
|
||||
cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
|
||||
CollapsedGepOp& cgo = *cgo_i;
|
||||
unsigned nextBasePtrReg = makeAnotherReg (Type::IntTy);
|
||||
unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
|
||||
|
||||
// If we didn't emit an add last time through the loop, we need to now so
|
||||
// that the base reg is updated appropriately.
|
||||
if (pendingAdd) {
|
||||
assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
|
||||
BuildMI(*MBB, IP, PPC32::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
|
||||
.addReg(pendingAddReg);
|
||||
basePtrReg = nextBasePtrReg;
|
||||
nextBasePtrReg = makeAnotherReg(Type::IntTy);
|
||||
pendingAddReg = 0;
|
||||
pendingAdd = false;
|
||||
}
|
||||
|
||||
if (cgo.isMul) {
|
||||
// We know the elementSize is a constant, so we can emit a constant mul
|
||||
// and then add it to the current base reg
|
||||
unsigned TmpReg = makeAnotherReg(Type::IntTy);
|
||||
doMultiplyConst(MBB, IP, TmpReg, cgo.index, cgo.size);
|
||||
BuildMI(*MBB, IP, PPC32::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
|
||||
.addReg(TmpReg);
|
||||
doMultiplyConst(MBB, IP, nextBasePtrReg, cgo.index, cgo.size);
|
||||
pendingAddReg = basePtrReg;
|
||||
pendingAdd = true;
|
||||
} else {
|
||||
// Try and generate an immediate addition if possible
|
||||
if (cgo.size->isNullValue()) {
|
||||
@ -3235,16 +3266,41 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
// the target, and save the current constant offset so the folding load or
|
||||
// store can try and use it as an immediate.
|
||||
if (GEPIsFolded) {
|
||||
BuildMI (BB, PPC32::OR, 2, TargetReg).addReg(basePtrReg).addReg(basePtrReg);
|
||||
// If this is a folded GEP and the last element was an index, then we need
|
||||
// to do some extra work to turn a shift/add/stw into a shift/stwx
|
||||
if (pendingAdd && 0 == remainder->getValue()) {
|
||||
assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
|
||||
*PendingAddReg = pendingAddReg;
|
||||
} else {
|
||||
*PendingAddReg = 0;
|
||||
if (pendingAdd) {
|
||||
unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
|
||||
assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
|
||||
BuildMI(*MBB, IP, PPC32::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
|
||||
.addReg(pendingAddReg);
|
||||
basePtrReg = nextBasePtrReg;
|
||||
}
|
||||
}
|
||||
BuildMI (*MBB, IP, PPC32::OR, 2, TargetReg).addReg(basePtrReg)
|
||||
.addReg(basePtrReg);
|
||||
*RemainderPtr = remainder;
|
||||
return;
|
||||
}
|
||||
|
||||
// If we still have a pending add at this point, emit it now
|
||||
if (pendingAdd) {
|
||||
unsigned TmpReg = makeAnotherReg(Type::IntTy);
|
||||
BuildMI(*MBB, IP, PPC32::ADD, 2, TmpReg).addReg(pendingAddReg)
|
||||
.addReg(basePtrReg);
|
||||
basePtrReg = TmpReg;
|
||||
}
|
||||
|
||||
// After we have processed all the indices, the result is left in
|
||||
// basePtrReg. Move it to the register where we were expected to
|
||||
// put the answer.
|
||||
if (remainder->isNullValue()) {
|
||||
BuildMI (BB, PPC32::OR, 2, TargetReg).addReg(basePtrReg).addReg(basePtrReg);
|
||||
BuildMI (*MBB, IP, PPC32::OR, 2, TargetReg).addReg(basePtrReg)
|
||||
.addReg(basePtrReg);
|
||||
} else if (canUseAsImmediateForOpcode(remainder, 0)) {
|
||||
BuildMI(*MBB, IP, PPC32::ADDI, 2, TargetReg).addReg(basePtrReg)
|
||||
.addSImm(remainder->getValue());
|
||||
|
||||
@ -1,9 +1,7 @@
|
||||
Currently unimplemented:
|
||||
* cast fp to bool
|
||||
* signed right shift of long by reg
|
||||
|
||||
Current bugs:
|
||||
* ulong to double. ahhh, here's the problem:
|
||||
TODO:
|
||||
* implement cast fp to bool
|
||||
* implement signed right shift by reg
|
||||
* fix ulong to double:
|
||||
floatdidf assumes signed longs. so if the high but of a ulong
|
||||
just happens to be set, you get the wrong sign. The fix for this
|
||||
is to call cmpdi2 to compare against zero, if so shift right by one,
|
||||
@ -19,10 +17,7 @@ Current bugs:
|
||||
shift right ulong a, 1 (we could use emitShift)
|
||||
call floatdidf
|
||||
fadd f1, f1, f1 (fp left shift by 1)
|
||||
* linking llvmg++ .s files with gcc instead of g++
|
||||
|
||||
Codegen improvements needed:
|
||||
* PowerPCPEI.cpp needs to save/restore regs in the opposite order
|
||||
* PowerPCPEI.cpp needs to be replaced by shiny new target hook
|
||||
* setCondInst needs to know branchless versions of seteq/setne/etc
|
||||
* cast elimination pass (uint -> sbyte -> short, kill the byte -> short)
|
||||
* should hint to the branch select pass that it doesn't need to print the
|
||||
@ -33,7 +28,7 @@ Codegen improvements needed:
|
||||
|
||||
Current hacks:
|
||||
* lazy insert of GlobalBaseReg definition at front of first MBB
|
||||
A prime candidate for sabre's "slightly above ISel" passes.
|
||||
A prime candidate for sabre's future "slightly above ISel" passes.
|
||||
* cast code is huge, unwieldy. Should probably be broken up into
|
||||
smaller pieces.
|
||||
* visitLoadInst is getting awfully cluttered as well.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user