From b64d92e29f38002e52a22fe36ea2d488968e3537 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 14 Dec 2010 00:37:44 +0000 Subject: [PATCH] Add stub for RAGreedy::trySplit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121736 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocGreedy.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index aab284805ea..005165eed69 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -83,6 +83,9 @@ private: bool checkUncachedInterference(LiveInterval &, unsigned); bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg); bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg); + + unsigned trySplit(LiveInterval&, AllocationOrder&, + SmallVectorImpl&); }; } // end anonymous namespace @@ -222,6 +225,15 @@ bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) { return reassignVReg(*Q.interferingVRegs()[0], PhysReg); } +/// trySplit - Try to split VirtReg or one of its interferences, making it +/// assignable. +/// @return Physreg when VirtReg may be assigned and/or new SplitVRegs. +unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, + SmallVectorImpl&SplitVRegs) { + NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled); + return 0; +} + unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl &SplitVRegs) { // Populate a list of physical register spill candidates. @@ -266,6 +278,10 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(), ReassignCands.end()); + unsigned PhysReg = trySplit(VirtReg, Order, SplitVRegs); + if (PhysReg || !SplitVRegs.empty()) + return PhysReg; + // Try to spill another interfering reg with less spill weight. NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled); //