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X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146257 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
parent
a73fb9adbb
commit
b653397dcd
@ -914,6 +914,17 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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if (Subtarget->hasSSE41orAVX()) {
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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setOperationAction(ISD::FRINT, MVT::f32, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::f64, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
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setOperationAction(ISD::FRINT, MVT::f64, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
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// FIXME: Do we need to handle scalar-to-vector here?
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setOperationAction(ISD::MUL, MVT::v4i32, Legal);
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@ -6134,6 +6134,27 @@ let Predicates = [HasAVX] in {
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defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
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int_x86_sse41_round_ss,
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int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
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def : Pat<(ffloor FR32:$src),
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(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
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def : Pat<(f64 (ffloor FR64:$src)),
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(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
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def : Pat<(f32 (fnearbyint FR32:$src)),
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(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
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def : Pat<(f64 (fnearbyint FR64:$src)),
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(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
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def : Pat<(f32 (fceil FR32:$src)),
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(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
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def : Pat<(f64 (fceil FR64:$src)),
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(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
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def : Pat<(f32 (frint FR32:$src)),
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(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
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def : Pat<(f64 (frint FR64:$src)),
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(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
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def : Pat<(f32 (ftrunc FR32:$src)),
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(VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
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def : Pat<(f64 (ftrunc FR64:$src)),
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(VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
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}
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defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
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@ -6143,6 +6164,27 @@ let Constraints = "$src1 = $dst" in
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defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
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int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
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def : Pat<(ffloor FR32:$src),
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(ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
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def : Pat<(f64 (ffloor FR64:$src)),
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(ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
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def : Pat<(f32 (fnearbyint FR32:$src)),
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(ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
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def : Pat<(f64 (fnearbyint FR64:$src)),
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(ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
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def : Pat<(f32 (fceil FR32:$src)),
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(ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
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def : Pat<(f64 (fceil FR64:$src)),
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(ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
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def : Pat<(f32 (frint FR32:$src)),
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(ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
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def : Pat<(f64 (frint FR64:$src)),
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(ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
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def : Pat<(f32 (ftrunc FR32:$src)),
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(ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
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def : Pat<(f64 (ftrunc FR64:$src)),
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(ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
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//===----------------------------------------------------------------------===//
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// SSE4.1 - Packed Bit Test
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//===----------------------------------------------------------------------===//
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132
test/CodeGen/X86/rounding-ops.ll
Normal file
132
test/CodeGen/X86/rounding-ops.ll
Normal file
@ -0,0 +1,132 @@
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; RUN: llc < %s -march=x86-64 -mattr=+sse41 | FileCheck -check-prefix=CHECK-SSE %s
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; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck -check-prefix=CHECK-AVX %s
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define float @test1(float %x) nounwind {
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%call = tail call float @floorf(float %x) nounwind readnone
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ret float %call
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; CHECK-SSE: test1:
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; CHECK-SSE: roundss $1
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; CHECK-AVX: test1:
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; CHECK-AVX: vroundss $1
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}
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declare float @floorf(float) nounwind readnone
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define double @test2(double %x) nounwind {
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%call = tail call double @floor(double %x) nounwind readnone
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ret double %call
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; CHECK-SSE: test2:
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; CHECK-SSE: roundsd $1
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; CHECK-AVX: test2:
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; CHECK-AVX: vroundsd $1
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}
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declare double @floor(double) nounwind readnone
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define float @test3(float %x) nounwind {
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%call = tail call float @nearbyintf(float %x) nounwind readnone
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ret float %call
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; CHECK-SSE: test3:
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; CHECK-SSE: roundss $12
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; CHECK-AVX: test3:
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; CHECK-AVX: vroundss $12
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}
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declare float @nearbyintf(float) nounwind readnone
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define double @test4(double %x) nounwind {
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%call = tail call double @nearbyint(double %x) nounwind readnone
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ret double %call
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; CHECK-SSE: test4:
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; CHECK-SSE: roundsd $12
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; CHECK-AVX: test4:
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; CHECK-AVX: vroundsd $12
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}
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declare double @nearbyint(double) nounwind readnone
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define float @test5(float %x) nounwind {
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%call = tail call float @ceilf(float %x) nounwind readnone
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ret float %call
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; CHECK-SSE: test5:
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; CHECK-SSE: roundss $2
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; CHECK-AVX: test5:
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; CHECK-AVX: vroundss $2
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}
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declare float @ceilf(float) nounwind readnone
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define double @test6(double %x) nounwind {
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%call = tail call double @ceil(double %x) nounwind readnone
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ret double %call
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; CHECK-SSE: test6:
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; CHECK-SSE: roundsd $2
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; CHECK-AVX: test6:
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; CHECK-AVX: vroundsd $2
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}
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declare double @ceil(double) nounwind readnone
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define float @test7(float %x) nounwind {
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%call = tail call float @rintf(float %x) nounwind readnone
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ret float %call
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; CHECK-SSE: test7:
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; CHECK-SSE: roundss $4
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; CHECK-AVX: test7:
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; CHECK-AVX: vroundss $4
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}
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declare float @rintf(float) nounwind readnone
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define double @test8(double %x) nounwind {
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%call = tail call double @rint(double %x) nounwind readnone
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ret double %call
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; CHECK-SSE: test8:
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; CHECK-SSE: roundsd $4
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; CHECK-AVX: test8:
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; CHECK-AVX: vroundsd $4
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}
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declare double @rint(double) nounwind readnone
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define float @test9(float %x) nounwind {
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%call = tail call float @truncf(float %x) nounwind readnone
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ret float %call
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; CHECK-SSE: test9:
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; CHECK-SSE: roundss $3
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; CHECK-AVX: test9:
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; CHECK-AVX: vroundss $3
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}
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declare float @truncf(float) nounwind readnone
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define double @test10(double %x) nounwind {
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%call = tail call double @trunc(double %x) nounwind readnone
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ret double %call
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; CHECK-SSE: test10:
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; CHECK-SSE: roundsd $3
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; CHECK-AVX: test10:
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; CHECK-AVX: vroundsd $3
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}
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declare double @trunc(double) nounwind readnone
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