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https://github.com/c64scene-ar/llvm-6502.git
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[SystemZ] Use "for (auto" a bit
Just the simple cases for now. There were a few knock-on changes of MachineBasicBlock *s to MachineBasicBlock &s. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -70,7 +70,7 @@ public:
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return "SystemZ Comparison Elimination";
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return "SystemZ Comparison Elimination";
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}
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}
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bool processBlock(MachineBasicBlock *MBB);
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bool processBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F);
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bool runOnMachineFunction(MachineFunction &F);
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private:
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private:
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@ -97,9 +97,8 @@ FunctionPass *llvm::createSystemZElimComparePass(SystemZTargetMachine &TM) {
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}
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}
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// Return true if CC is live out of MBB.
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// Return true if CC is live out of MBB.
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static bool isCCLiveOut(MachineBasicBlock *MBB) {
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static bool isCCLiveOut(MachineBasicBlock &MBB) {
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI)
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SE = MBB->succ_end(); SI != SE; ++SI)
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if ((*SI)->isLiveIn(SystemZ::CC))
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if ((*SI)->isLiveIn(SystemZ::CC))
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return true;
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return true;
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return false;
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return false;
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@ -328,8 +327,8 @@ optimizeCompareZero(MachineInstr *Compare,
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// Search back for CC results that are based on the first operand.
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// Search back for CC results that are based on the first operand.
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unsigned SrcReg = Compare->getOperand(0).getReg();
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unsigned SrcReg = Compare->getOperand(0).getReg();
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unsigned SrcSubReg = Compare->getOperand(0).getSubReg();
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unsigned SrcSubReg = Compare->getOperand(0).getSubReg();
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MachineBasicBlock *MBB = Compare->getParent();
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MachineBasicBlock &MBB = *Compare->getParent();
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MachineBasicBlock::iterator MBBI = Compare, MBBE = MBB->begin();
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MachineBasicBlock::iterator MBBI = Compare, MBBE = MBB.begin();
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Reference CCRefs;
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Reference CCRefs;
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Reference SrcRefs;
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Reference SrcRefs;
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while (MBBI != MBBE) {
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while (MBBI != MBBE) {
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@ -424,7 +423,7 @@ fuseCompareAndBranch(MachineInstr *Compare,
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// Process all comparison instructions in MBB. Return true if something
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// Process all comparison instructions in MBB. Return true if something
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// changed.
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// changed.
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bool SystemZElimCompare::processBlock(MachineBasicBlock *MBB) {
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bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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bool Changed = false;
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// Walk backwards through the block looking for comparisons, recording
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// Walk backwards through the block looking for comparisons, recording
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@ -432,8 +431,8 @@ bool SystemZElimCompare::processBlock(MachineBasicBlock *MBB) {
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// instructions before it.
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// instructions before it.
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bool CompleteCCUsers = !isCCLiveOut(MBB);
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bool CompleteCCUsers = !isCCLiveOut(MBB);
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SmallVector<MachineInstr *, 4> CCUsers;
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SmallVector<MachineInstr *, 4> CCUsers;
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MachineBasicBlock::iterator MBBI = MBB->end();
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MachineBasicBlock::iterator MBBI = MBB.end();
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while (MBBI != MBB->begin()) {
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while (MBBI != MBB.begin()) {
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MachineInstr *MI = --MBBI;
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MachineInstr *MI = --MBBI;
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if (CompleteCCUsers &&
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if (CompleteCCUsers &&
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MI->isCompare() &&
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MI->isCompare() &&
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@ -463,9 +462,8 @@ bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) {
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TRI = &TII->getRegisterInfo();
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TRI = &TII->getRegisterInfo();
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bool Changed = false;
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bool Changed = false;
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for (MachineFunction::iterator MFI = F.begin(), MFE = F.end();
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for (auto &MBB : F)
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MFI != MFE; ++MFI)
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Changed |= processBlock(MBB);
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Changed |= processBlock(MFI);
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return Changed;
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return Changed;
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}
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}
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@ -336,9 +336,8 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
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MCSymbol *GPRSaveLabel = MMI.getContext().CreateTempSymbol();
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MCSymbol *GPRSaveLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, DL,
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BuildMI(MBB, MBBI, DL,
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ZII->get(TargetOpcode::PROLOG_LABEL)).addSym(GPRSaveLabel);
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ZII->get(TargetOpcode::PROLOG_LABEL)).addSym(GPRSaveLabel);
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for (std::vector<CalleeSavedInfo>::const_iterator
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for (auto &Save : CSI) {
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I = CSI.begin(), E = CSI.end(); I != E; ++I) {
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unsigned Reg = Save.getReg();
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unsigned Reg = I->getReg();
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if (SystemZ::GR64BitRegClass.contains(Reg)) {
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if (SystemZ::GR64BitRegClass.contains(Reg)) {
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int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
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int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
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MMI.addFrameInst(MCCFIInstruction::createOffset(
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MMI.addFrameInst(MCCFIInstruction::createOffset(
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@ -378,16 +377,14 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
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// Mark the FramePtr as live at the beginning of every block except
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// Mark the FramePtr as live at the beginning of every block except
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// the entry block. (We'll have marked R11 as live on entry when
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// the entry block. (We'll have marked R11 as live on entry when
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// saving the GPRs.)
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// saving the GPRs.)
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for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
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for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
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I != E; ++I)
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I->addLiveIn(SystemZ::R11D);
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I->addLiveIn(SystemZ::R11D);
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}
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}
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// Skip over the FPR saves.
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// Skip over the FPR saves.
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MCSymbol *FPRSaveLabel = 0;
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MCSymbol *FPRSaveLabel = 0;
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for (std::vector<CalleeSavedInfo>::const_iterator
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for (auto &Save : CSI) {
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I = CSI.begin(), E = CSI.end(); I != E; ++I) {
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unsigned Reg = Save.getReg();
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unsigned Reg = I->getReg();
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if (SystemZ::FP64BitRegClass.contains(Reg)) {
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if (SystemZ::FP64BitRegClass.contains(Reg)) {
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if (MBBI != MBB.end() &&
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if (MBBI != MBB.end() &&
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(MBBI->getOpcode() == SystemZ::STD ||
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(MBBI->getOpcode() == SystemZ::STD ||
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@ -399,10 +396,10 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
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// Add CFI for the this save.
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// Add CFI for the this save.
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if (!FPRSaveLabel)
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if (!FPRSaveLabel)
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FPRSaveLabel = MMI.getContext().CreateTempSymbol();
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FPRSaveLabel = MMI.getContext().CreateTempSymbol();
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unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
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unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
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int64_t Offset = getFrameIndexOffset(MF, I->getFrameIdx());
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int64_t Offset = getFrameIndexOffset(MF, Save.getFrameIdx());
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MMI.addFrameInst(MCCFIInstruction::createOffset(
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MMI.addFrameInst(MCCFIInstruction::createOffset(
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FPRSaveLabel, Reg, SPOffsetFromCFA + Offset));
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FPRSaveLabel, DwarfReg, SPOffsetFromCFA + Offset));
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}
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}
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}
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}
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// Complete the CFI for the FPR saves, modelling them as taking effect
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// Complete the CFI for the FPR saves, modelling them as taking effect
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@ -1284,8 +1284,7 @@ static unsigned reverseCCMask(unsigned CCMask) {
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static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
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static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
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if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
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if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
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C.CCMask == SystemZ::CCMASK_CMP_NE) {
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C.CCMask == SystemZ::CCMASK_CMP_NE) {
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for (SDNode::use_iterator I = C.Op0->use_begin(), E = C.Op0->use_end();
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for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
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I != E; ++I) {
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SDNode *N = *I;
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SDNode *N = *I;
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if (N->getOpcode() == ISD::SUB &&
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if (N->getOpcode() == ISD::SUB &&
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((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
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((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
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@ -1305,8 +1304,7 @@ static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
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static void adjustForFNeg(Comparison &C) {
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static void adjustForFNeg(Comparison &C) {
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ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
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ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
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if (C1 && C1->isZero()) {
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if (C1 && C1->isZero()) {
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for (SDNode::use_iterator I = C.Op0->use_begin(), E = C.Op0->use_end();
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for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
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I != E; ++I) {
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SDNode *N = *I;
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SDNode *N = *I;
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if (N->getOpcode() == ISD::FNEG) {
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if (N->getOpcode() == ISD::FNEG) {
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C.Op0 = SDValue(N, 0);
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C.Op0 = SDValue(N, 0);
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@ -1333,8 +1331,7 @@ static void adjustForLTGFR(Comparison &C) {
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if (C1 && C1->getZExtValue() == 32) {
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if (C1 && C1->getZExtValue() == 32) {
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SDValue ShlOp0 = C.Op0.getOperand(0);
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SDValue ShlOp0 = C.Op0.getOperand(0);
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// See whether X has any SIGN_EXTEND_INREG uses.
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// See whether X has any SIGN_EXTEND_INREG uses.
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for (SDNode::use_iterator I = ShlOp0->use_begin(), E = ShlOp0->use_end();
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for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
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I != E; ++I) {
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SDNode *N = *I;
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SDNode *N = *I;
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if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
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if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
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cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
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cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
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@ -321,9 +321,8 @@ bool SystemZLongBranch::mustRelaxBranch(const TerminatorInfo &Terminator,
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// Return true if, under current assumptions, any terminator needs
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// Return true if, under current assumptions, any terminator needs
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// to be relaxed.
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// to be relaxed.
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bool SystemZLongBranch::mustRelaxABranch() {
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bool SystemZLongBranch::mustRelaxABranch() {
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for (SmallVectorImpl<TerminatorInfo>::iterator TI = Terminators.begin(),
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for (auto &Terminator : Terminators)
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TE = Terminators.end(); TI != TE; ++TI)
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if (mustRelaxBranch(Terminator, Terminator.Address))
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if (mustRelaxBranch(*TI, TI->Address))
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return true;
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return true;
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return false;
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return false;
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}
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}
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@ -333,10 +332,9 @@ bool SystemZLongBranch::mustRelaxABranch() {
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void SystemZLongBranch::setWorstCaseAddresses() {
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void SystemZLongBranch::setWorstCaseAddresses() {
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SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
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SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
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BlockPosition Position(MF->getAlignment());
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BlockPosition Position(MF->getAlignment());
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for (SmallVectorImpl<MBBInfo>::iterator BI = MBBs.begin(), BE = MBBs.end();
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for (auto &Block : MBBs) {
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BI != BE; ++BI) {
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skipNonTerminators(Position, Block);
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skipNonTerminators(Position, *BI);
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for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
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for (unsigned BTI = 0, BTE = BI->NumTerminators; BTI != BTE; ++BTI) {
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skipTerminator(Position, *TI, true);
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skipTerminator(Position, *TI, true);
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++TI;
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++TI;
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}
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}
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@ -435,10 +433,9 @@ void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
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void SystemZLongBranch::relaxBranches() {
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void SystemZLongBranch::relaxBranches() {
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SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
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SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
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BlockPosition Position(MF->getAlignment());
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BlockPosition Position(MF->getAlignment());
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for (SmallVectorImpl<MBBInfo>::iterator BI = MBBs.begin(), BE = MBBs.end();
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for (auto &Block : MBBs) {
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BI != BE; ++BI) {
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skipNonTerminators(Position, Block);
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skipNonTerminators(Position, *BI);
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for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
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for (unsigned BTI = 0, BTE = BI->NumTerminators; BTI != BTE; ++BTI) {
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assert(Position.Address <= TI->Address &&
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assert(Position.Address <= TI->Address &&
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"Addresses shouldn't go forwards");
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"Addresses shouldn't go forwards");
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if (mustRelaxBranch(*TI, Position.Address))
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if (mustRelaxBranch(*TI, Position.Address))
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@ -30,7 +30,7 @@ public:
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return "SystemZ Instruction Shortening";
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return "SystemZ Instruction Shortening";
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}
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}
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bool processBlock(MachineBasicBlock *MBB);
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bool processBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F);
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bool runOnMachineFunction(MachineFunction &F);
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private:
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private:
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@ -98,16 +98,15 @@ bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned *GPRMap,
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}
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}
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// Process all instructions in MBB. Return true if something changed.
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// Process all instructions in MBB. Return true if something changed.
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bool SystemZShortenInst::processBlock(MachineBasicBlock *MBB) {
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bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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bool Changed = false;
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// Work out which words are live on exit from the block.
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// Work out which words are live on exit from the block.
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unsigned LiveLow = 0;
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unsigned LiveLow = 0;
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unsigned LiveHigh = 0;
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unsigned LiveHigh = 0;
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI) {
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SE = MBB->succ_end(); SI != SE; ++SI) {
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for (auto LI = (*SI)->livein_begin(), LE = (*SI)->livein_end();
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for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
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LI != LE; ++LI) {
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LE = (*SI)->livein_end(); LI != LE; ++LI) {
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unsigned Reg = *LI;
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unsigned Reg = *LI;
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assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
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assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
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LiveLow |= LowGPRs[Reg];
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LiveLow |= LowGPRs[Reg];
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@ -116,8 +115,7 @@ bool SystemZShortenInst::processBlock(MachineBasicBlock *MBB) {
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}
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}
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// Iterate backwards through the block looking for instructions to change.
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// Iterate backwards through the block looking for instructions to change.
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for (MachineBasicBlock::reverse_iterator MBBI = MBB->rbegin(),
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for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
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MBBE = MBB->rend(); MBBI != MBBE; ++MBBI) {
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MachineInstr &MI = *MBBI;
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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unsigned Opcode = MI.getOpcode();
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if (Opcode == SystemZ::IILF)
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if (Opcode == SystemZ::IILF)
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@ -128,8 +126,8 @@ bool SystemZShortenInst::processBlock(MachineBasicBlock *MBB) {
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SystemZ::LLIHH);
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SystemZ::LLIHH);
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unsigned UsedLow = 0;
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unsigned UsedLow = 0;
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unsigned UsedHigh = 0;
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unsigned UsedHigh = 0;
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for (MachineInstr::mop_iterator MOI = MI.operands_begin(),
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for (auto MOI = MI.operands_begin(), MOE = MI.operands_end();
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MOE = MI.operands_end(); MOI != MOE; ++MOI) {
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MOI != MOE; ++MOI) {
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MachineOperand &MO = *MOI;
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MachineOperand &MO = *MOI;
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if (MO.isReg()) {
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if (MO.isReg()) {
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if (unsigned Reg = MO.getReg()) {
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if (unsigned Reg = MO.getReg()) {
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@ -155,9 +153,8 @@ bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
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TII = static_cast<const SystemZInstrInfo *>(F.getTarget().getInstrInfo());
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TII = static_cast<const SystemZInstrInfo *>(F.getTarget().getInstrInfo());
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bool Changed = false;
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bool Changed = false;
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for (MachineFunction::iterator MFI = F.begin(), MFE = F.end();
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for (auto &MBB : F)
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MFI != MFE; ++MFI)
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Changed |= processBlock(MBB);
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Changed |= processBlock(MFI);
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return Changed;
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return Changed;
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}
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}
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