mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
Fix some 80-col. violations I introduced with the A2 PPC64 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
19aa2b5015
commit
b66e943d4c
@ -90,7 +90,8 @@ def : Processor<"g5", G5Itineraries,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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Feature64Bit
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/*, Feature64BitRegs */]>;
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def : Processor<"ppc", G3Itineraries, [Directive32]>;
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def : Processor<"ppc64", G5Itineraries,
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[Directive64, FeatureAltivec,
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@ -60,7 +60,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6,
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FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6],
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[CR_Bypass, GPR_Bypass, FPR_Bypass], [
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InstrItinData<IntGeneral , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntGeneral , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -70,7 +71,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntCompare , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntCompare , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -80,7 +82,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntDivW , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntDivW , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -90,7 +93,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>],
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[53, 7, 7],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMFFS , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntMFFS , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -100,7 +104,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMTFSB0 , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntMTFSB0 , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -110,7 +115,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHW , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntMulHW , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -120,7 +126,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHWU , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntMulHWU , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -130,7 +137,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulLI , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntMulLI , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -140,7 +148,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[15, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntRotate , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntRotate , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -150,7 +159,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntShift , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntShift , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -160,7 +170,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntTrapW , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<IntTrapW , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -170,7 +181,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<BrB , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<BrB , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -180,7 +192,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[15, 7, 7],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<BrCR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<BrCR , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -190,7 +203,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<BrMCR , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -200,7 +214,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCRX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<BrMCRX , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -210,7 +225,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBA , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStDCBA , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -220,7 +236,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[13, 11],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStDCBF , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStDCBF , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -230,7 +247,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[13, 11],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStDCBI , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStDCBI , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -240,7 +258,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[13, 11],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStLoad , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStLoad , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -250,7 +269,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7],
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStStore , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStStore , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -260,7 +280,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[13, 7],
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStICBI , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStICBI , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -270,7 +291,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStUX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStUX , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -280,7 +302,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7, 7],
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[NoBypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<LdStLFD , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStLFD , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -290,7 +313,8 @@ def PPCA2Itineraries : ProcessorItineraries<
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7, 7],
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[FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLFDU , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrItinData<LdStLFDU , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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@ -300,7 +324,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7, 7],
|
||||
[FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLHA , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStLHA , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -310,7 +335,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -320,7 +346,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLWARX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStLWARX , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||||
@ -330,7 +357,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[26, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTD , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStSTD , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -340,7 +368,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[13, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||||
@ -350,7 +379,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[26, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTD , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStSTD , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -360,7 +390,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[13, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||||
@ -370,7 +401,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[26, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTWCX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStSTWCX , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||||
@ -380,7 +412,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[26, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSync , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<LdStSync , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -388,7 +421,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>,
|
||||
InstrItinData<SprISYNC , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprISYNC , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -396,7 +430,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
|
||||
InstrItinData<SprMFSR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMFSR , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -406,7 +441,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[15, 7],
|
||||
[GPR_Bypass, NoBypass]>,
|
||||
InstrItinData<SprMTMSR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMTMSR , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -416,7 +452,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[15, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<SprMTSR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMTSR , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -426,7 +463,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[15, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<SprTLBSYNC , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprTLBSYNC , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -434,7 +472,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
|
||||
InstrItinData<SprMFCR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMFCR , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -444,7 +483,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[10, 7],
|
||||
[GPR_Bypass, CR_Bypass]>,
|
||||
InstrItinData<SprMFMSR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMFMSR , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -454,7 +494,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[15, 7],
|
||||
[GPR_Bypass, NoBypass]>,
|
||||
InstrItinData<SprMFSPR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMFSPR , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -464,7 +505,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[15, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<SprMFTB , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMFTB , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -474,7 +516,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||||
[29, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<SprMTSPR , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMTSPR , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -484,7 +527,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[15, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<SprMTSRIN , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprMTSRIN , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -494,7 +538,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||||
[29, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<SprRFI , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprRFI , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -504,7 +549,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||||
[29, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<SprSC , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<SprSC , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -514,7 +560,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||||
[29, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<FPGeneral , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<FPGeneral , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -524,7 +571,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||||
[15, 7, 7],
|
||||
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPCompare , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<FPCompare , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -534,40 +582,53 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||||
[13, 7, 7],
|
||||
[CR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPDivD , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<FPDivD , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>,
|
||||
InstrStage<71, [FEX1], 0>, InstrStage<71, [FEX2], 0>,
|
||||
InstrStage<71, [FEX3], 0>, InstrStage<71, [FEX4], 0>,
|
||||
InstrStage<71, [FEX5], 0>, InstrStage<71, [FEX6]>],
|
||||
InstrStage<71, [FEX1], 0>,
|
||||
InstrStage<71, [FEX2], 0>,
|
||||
InstrStage<71, [FEX3], 0>,
|
||||
InstrStage<71, [FEX4], 0>,
|
||||
InstrStage<71, [FEX5], 0>,
|
||||
InstrStage<71, [FEX6]>],
|
||||
[86, 7, 7],
|
||||
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPDivS , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<FPDivS , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>,
|
||||
InstrStage<58, [FEX1], 0>, InstrStage<58, [FEX2], 0>,
|
||||
InstrStage<58, [FEX3], 0>, InstrStage<58, [FEX4], 0>,
|
||||
InstrStage<58, [FEX5], 0>, InstrStage<58, [FEX6]>],
|
||||
InstrStage<58, [FEX1], 0>,
|
||||
InstrStage<58, [FEX2], 0>,
|
||||
InstrStage<58, [FEX3], 0>,
|
||||
InstrStage<58, [FEX4], 0>,
|
||||
InstrStage<58, [FEX5], 0>,
|
||||
InstrStage<58, [FEX6]>],
|
||||
[73, 7, 7],
|
||||
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPSqrt , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<FPSqrt , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>,
|
||||
InstrStage<68, [FEX1], 0>, InstrStage<68, [FEX2], 0>,
|
||||
InstrStage<68, [FEX3], 0>, InstrStage<68, [FEX4], 0>,
|
||||
InstrStage<68, [FEX5], 0>, InstrStage<68, [FEX6]>],
|
||||
InstrStage<68, [FEX1], 0>,
|
||||
InstrStage<68, [FEX2], 0>,
|
||||
InstrStage<68, [FEX3], 0>,
|
||||
InstrStage<68, [FEX4], 0>,
|
||||
InstrStage<68, [FEX5], 0>,
|
||||
InstrStage<68, [FEX6]>],
|
||||
[86, 7], // FIXME: should be [86, 7] for double
|
||||
// and [82, 7] for single. Likewise,
|
||||
// the FEX? cycle count should be 68
|
||||
// for double and 64 for single.
|
||||
[NoBypass, FPR_Bypass]>,
|
||||
InstrItinData<FPFused , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<FPFused , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
@ -577,7 +638,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||||
[15, 7, 7, 7],
|
||||
[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPRes , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrItinData<FPRes , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user