From b67284057ee130114055309eabe0bcd1af13777d Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Fri, 13 Feb 2009 02:25:56 +0000 Subject: [PATCH] Remove refs to non-DebugLoc versions of BuildMI from ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMConstantIslandPass.cpp | 22 ++++++++++++++-------- lib/Target/ARM/ARMISelLowering.cpp | 5 +++-- lib/Target/ARM/ARMInstrInfo.cpp | 13 ++++++++----- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 20 +++++++++++++------- lib/Target/ARM/ARMRegisterInfo.h | 3 ++- 5 files changed, 40 insertions(+), 23 deletions(-) diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index 5ecb28e9ec1..746d5edf17c 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -301,7 +301,7 @@ void ARMConstantIslands::DoInitialPlacement(MachineFunction &Fn, // aligned. assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!"); MachineInstr *CPEMI = - BuildMI(BB, TII->get(ARM::CONSTPOOL_ENTRY)) + BuildMI(BB, DebugLoc::getUnknownLoc(), TII->get(ARM::CONSTPOOL_ENTRY)) .addImm(i).addConstantPoolIndex(i).addImm(Size); CPEMIs.push_back(CPEMI); @@ -567,7 +567,10 @@ MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) { // Add an unconditional branch from OrigBB to NewBB. // Note the new unconditional branch is not being recorded. - BuildMI(OrigBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB); + // There doesn't seem to be meaningful DebugInfo available; this doesn't + // correspond to anything in the source. + BuildMI(OrigBB, DebugLoc::getUnknownLoc(), + TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB); NumSplit++; // Update the CFG. All succs of OrigBB are now succs of NewBB. @@ -931,7 +934,8 @@ void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex, // targets will be exchanged, and the altered branch may be out of // range, so the machinery has to know about it. int UncondBr = isThumb ? ARM::tB : ARM::B; - BuildMI(UserMBB, TII->get(UncondBr)).addMBB(*NewMBB); + BuildMI(UserMBB, DebugLoc::getUnknownLoc(), + TII->get(UncondBr)).addMBB(*NewMBB); unsigned MaxDisp = getUnconditionalBrDisp(UncondBr); ImmBranches.push_back(ImmBranch(&UserMBB->back(), MaxDisp, false, UncondBr)); @@ -1042,7 +1046,8 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn, // Now that we have an island to add the CPE to, clone the original CPE and // add it to the island. - U.CPEMI = BuildMI(NewIsland, TII->get(ARM::CONSTPOOL_ENTRY)) + U.CPEMI = BuildMI(NewIsland, DebugLoc::getUnknownLoc(), + TII->get(ARM::CONSTPOOL_ENTRY)) .addImm(ID).addConstantPoolIndex(CPI).addImm(Size); CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1)); NumCPEs++; @@ -1240,11 +1245,12 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) { // Insert a new conditional branch and a new unconditional branch. // Also update the ImmBranch as well as adding a new entry for the new branch. - BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB) - .addImm(CC).addReg(CCReg); + BuildMI(MBB, DebugLoc::getUnknownLoc(), + TII->get(MI->getOpcode())) + .addMBB(NextBB).addImm(CC).addReg(CCReg); Br.MI = &MBB->back(); BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); - BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB); + BuildMI(MBB, DebugLoc::getUnknownLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); @@ -1268,7 +1274,7 @@ bool ARMConstantIslands::UndoLRSpillRestore() { if (MI->getOpcode() == ARM::tPOP_RET && MI->getOperand(0).getReg() == ARM::PC && MI->getNumExplicitOperands() == 1) { - BuildMI(MI->getParent(), TII->get(ARM::tBX_RET)); + BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)); MI->eraseFromParent(); MadeChange = true; } diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 0ca9231c280..41852fa594e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1498,6 +1498,7 @@ MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); case ARM::tMOVCCr: { @@ -1519,7 +1520,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) + BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -1547,7 +1548,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 891d3a4a7eb..9dc0785789b 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -147,10 +147,11 @@ void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, const MachineInstr *Orig) const { + DebugLoc dl = Orig->getDebugLoc(); if (Orig->getOpcode() == ARM::MOVi2pieces) { RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(), Orig->getOperand(2).getImm(), - Orig->getOperand(3).getReg(), this, false); + Orig->getOperand(3).getReg(), this, false, dl); return; } @@ -447,6 +448,8 @@ unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B; @@ -459,17 +462,17 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *T if (FBB == 0) { if (Cond.empty()) // Unconditional branch? - BuildMI(&MBB, get(BOpc)).addMBB(TBB); + BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); else - BuildMI(&MBB, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); return 1; } // Two-way conditional branch. - BuildMI(&MBB, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); - BuildMI(&MBB, get(BOpc)).addMBB(FBB); + BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); return 2; } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 27fec1fc60d..710bc3e90ef 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -116,6 +116,8 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, SmallVector, 8> &Regs, const TargetInstrInfo *TII) { + // FIXME would it be better to take a DL from one of the loads arbitrarily? + DebugLoc dl = DebugLoc::getUnknownLoc(); // Only a single register to load / store. Don't bother. unsigned NumRegs = Regs.size(); if (NumRegs <= 1) @@ -156,7 +158,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, if (ImmedOffset == -1) return false; // Probably not worth it then. - BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase) + BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) .addReg(Base, false, false, BaseKill).addImm(ImmedOffset) .addImm(Pred).addReg(PredReg).addReg(0); Base = NewBase; @@ -167,9 +169,11 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD; Opcode = getLoadStoreMultipleOpcode(Opcode); MachineInstrBuilder MIB = (isAM4) - ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill) + ? BuildMI(MBB, MBBI, dl, TII->get(Opcode)) + .addReg(Base, false, false, BaseKill) .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg) - : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill) + : BuildMI(MBB, MBBI, dl, TII->get(Opcode)) + .addReg(Base, false, false, BaseKill) .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs)) .addImm(Pred).addReg(PredReg); for (unsigned i = 0; i != NumRegs; ++i) @@ -450,6 +454,7 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB, bool BaseKill = MI->getOperand(1).isKill(); unsigned Bytes = getLSMultipleTransferSize(MI); int Opcode = MI->getOpcode(); + DebugLoc dl = MI->getDebugLoc(); bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR; if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) || (!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)) @@ -510,24 +515,25 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB, if (isLd) { if (isAM2) // LDR_PRE, LDR_POST; - BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg()) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) .addReg(Base, true) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FLDMS, FLDMD - BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) + .addReg(Base, false, false, BaseKill) .addImm(Offset).addImm(Pred).addReg(PredReg) .addReg(MI->getOperand(0).getReg(), true); } else { MachineOperand &MO = MI->getOperand(0); if (isAM2) // STR_PRE, STR_POST; - BuildMI(MBB, MBBI, TII->get(NewOpc), Base) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) .addReg(MO.getReg(), false, false, MO.isKill()) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FSTMS, FSTMD - BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset) .addImm(Pred).addReg(PredReg) .addReg(MO.getReg(), false, false, MO.isKill()); } diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h index 68761298669..db7ee5e8759 100644 --- a/lib/Target/ARM/ARMRegisterInfo.h +++ b/lib/Target/ARM/ARMRegisterInfo.h @@ -38,7 +38,8 @@ public: MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Val, unsigned Pred, unsigned PredReg, - const TargetInstrInfo *TII, bool isThumb) const; + const TargetInstrInfo *TII, bool isThumb, + DebugLoc dl) const; /// getRegisterNumbering - Given the enum value for some register, e.g. /// ARM::LR, return the number that it corresponds to (e.g. 14).