mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
[NVPTX] Clean up handling of formal arguments and enable generation of vector parameter loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185172 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
00df125228
commit
b673665143
@ -1066,12 +1066,16 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
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const Function *F = MF.getFunction();
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const AttributeSet &PAL = F->getAttributes();
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const TargetLowering *TLI = nvTM->getTargetLowering();
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SDValue Root = DAG.getRoot();
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std::vector<SDValue> OutChains;
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bool isKernel = llvm::isKernelFunction(*F);
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bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
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assert(isABI && "Non-ABI compilation is not supported");
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if (!isABI)
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return Chain;
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std::vector<Type *> argTypes;
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std::vector<const Argument *> theArgs;
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@ -1080,15 +1084,20 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
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theArgs.push_back(I);
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argTypes.push_back(I->getType());
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}
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//assert(argTypes.size() == Ins.size() &&
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// "Ins types and function types did not match");
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// argTypes.size() (or theArgs.size()) and Ins.size() need not match.
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// Ins.size() will be larger
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// * if there is an aggregate argument with multiple fields (each field
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// showing up separately in Ins)
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// * if there is a vector argument with more than typical vector-length
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// elements (generally if more than 4) where each vector element is
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// individually present in Ins.
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// So a different index should be used for indexing into Ins.
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// See similar issue in LowerCall.
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unsigned InsIdx = 0;
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int idx = 0;
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for (unsigned i = 0, e = argTypes.size(); i != e; ++i, ++idx) {
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for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
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Type *Ty = argTypes[i];
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EVT ObjectVT = getValueType(Ty);
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//assert(ObjectVT == Ins[i].VT &&
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// "Ins type did not match function type");
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// If the kernel argument is image*_t or sampler_t, convert it to
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// a i32 constant holding the parameter position. This can later
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@ -1104,142 +1113,220 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
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if (theArgs[i]->use_empty()) {
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// argument is dead
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if (ObjectVT.isVector()) {
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EVT EltVT = ObjectVT.getVectorElementType();
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unsigned NumElts = ObjectVT.getVectorNumElements();
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for (unsigned vi = 0; vi < NumElts; ++vi) {
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InVals.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
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if (Ty->isAggregateType()) {
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SmallVector<EVT, 16> vtparts;
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ComputeValueVTs(*this, Ty, vtparts);
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assert(vtparts.size() > 0 && "empty aggregate type not expected");
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for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
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++parti) {
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EVT partVT = vtparts[parti];
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InVals.push_back(DAG.getNode(ISD::UNDEF, dl, partVT));
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++InsIdx;
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}
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} else {
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InVals.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
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if (vtparts.size() > 0)
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--InsIdx;
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continue;
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}
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if (Ty->isVectorTy()) {
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EVT ObjectVT = getValueType(Ty);
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unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
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for (unsigned parti = 0; parti < NumRegs; ++parti) {
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InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
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++InsIdx;
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}
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if (NumRegs > 0)
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--InsIdx;
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continue;
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}
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InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
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continue;
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}
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// In the following cases, assign a node order of "idx+1"
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// to newly created nodes. The SDNOdes for params have to
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// to newly created nodes. The SDNodes for params have to
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// appear in the same order as their order of appearance
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// in the original function. "idx+1" holds that order.
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if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
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if (ObjectVT.isVector()) {
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unsigned NumElts = ObjectVT.getVectorNumElements();
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EVT EltVT = ObjectVT.getVectorElementType();
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unsigned Offset = 0;
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for (unsigned vi = 0; vi < NumElts; ++vi) {
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SDValue A = getParamSymbol(DAG, idx, getPointerTy());
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SDValue B = DAG.getIntPtrConstant(Offset);
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SDValue Addr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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//getParamSymbol(DAG, idx, EltVT),
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//DAG.getConstant(Offset, getPointerTy()));
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A, B);
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Value *SrcValue = Constant::getNullValue(PointerType::get(
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EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
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SDValue Ld = DAG.getLoad(
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EltVT, dl, Root, Addr, MachinePointerInfo(SrcValue), false, false,
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false,
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TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
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Offset += EltVT.getStoreSizeInBits() / 8;
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InVals.push_back(Ld);
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if (Ty->isAggregateType()) {
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SmallVector<EVT, 16> vtparts;
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SmallVector<uint64_t, 16> offsets;
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ComputeValueVTs(*this, Ty, vtparts, &offsets, 0);
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assert(vtparts.size() > 0 && "empty aggregate type not expected");
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bool aggregateIsPacked = false;
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if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
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aggregateIsPacked = STy->isPacked();
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SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
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for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
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++parti) {
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EVT partVT = vtparts[parti];
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Value *srcValue = Constant::getNullValue(
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PointerType::get(partVT.getTypeForEVT(F->getContext()),
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llvm::ADDRESS_SPACE_PARAM));
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SDValue srcAddr =
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DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
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DAG.getConstant(offsets[parti], getPointerTy()));
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unsigned partAlign =
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aggregateIsPacked ? 1
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: TD->getABITypeAlignment(
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partVT.getTypeForEVT(F->getContext()));
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SDValue p = DAG.getLoad(partVT, dl, Root, srcAddr,
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MachinePointerInfo(srcValue), false, false,
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true, partAlign);
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if (p.getNode())
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p.getNode()->setIROrder(idx + 1);
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InVals.push_back(p);
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++InsIdx;
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}
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if (vtparts.size() > 0)
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--InsIdx;
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continue;
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}
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// A plain scalar.
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if (isABI || isKernel) {
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// If ABI, load from the param symbol
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if (Ty->isVectorTy()) {
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EVT ObjectVT = getValueType(Ty);
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SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
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// Conjure up a value that we can get the address space from.
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// FIXME: Using a constant here is a hack.
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Value *srcValue = Constant::getNullValue(
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PointerType::get(ObjectVT.getTypeForEVT(F->getContext()),
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llvm::ADDRESS_SPACE_PARAM));
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SDValue p = DAG.getLoad(
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ObjectVT, dl, Root, Arg, MachinePointerInfo(srcValue), false, false,
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false,
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TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
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if (p.getNode())
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p.getNode()->setIROrder(idx + 1);
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InVals.push_back(p);
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} else {
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// If no ABI, just move the param symbol
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SDValue Arg = getParamSymbol(DAG, idx, ObjectVT);
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SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
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if (p.getNode())
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p.getNode()->setIROrder(idx + 1);
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InVals.push_back(p);
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unsigned NumElts = ObjectVT.getVectorNumElements();
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assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
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"Vector was not scalarized");
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unsigned Ofst = 0;
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EVT EltVT = ObjectVT.getVectorElementType();
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// V1 load
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// f32 = load ...
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if (NumElts == 1) {
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// We only have one element, so just directly load it
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Value *SrcValue = Constant::getNullValue(PointerType::get(
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EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
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SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
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DAG.getConstant(Ofst, getPointerTy()));
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SDValue P = DAG.getLoad(
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EltVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
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false, true,
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TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
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if (P.getNode())
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P.getNode()->setIROrder(idx + 1);
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InVals.push_back(P);
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Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
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++InsIdx;
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} else if (NumElts == 2) {
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// V2 load
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// f32,f32 = load ...
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EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
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Value *SrcValue = Constant::getNullValue(PointerType::get(
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VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
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SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
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DAG.getConstant(Ofst, getPointerTy()));
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SDValue P = DAG.getLoad(
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VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
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false, true,
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TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
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if (P.getNode())
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P.getNode()->setIROrder(idx + 1);
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SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
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DAG.getIntPtrConstant(0));
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SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
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DAG.getIntPtrConstant(1));
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InVals.push_back(Elt0);
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InVals.push_back(Elt1);
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Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
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InsIdx += 2;
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} else {
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// V4 loads
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// We have at least 4 elements (<3 x Ty> expands to 4 elements) and
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// the
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// vector will be expanded to a power of 2 elements, so we know we can
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// always round up to the next multiple of 4 when creating the vector
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// loads.
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// e.g. 4 elem => 1 ld.v4
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// 6 elem => 2 ld.v4
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// 8 elem => 2 ld.v4
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// 11 elem => 3 ld.v4
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unsigned VecSize = 4;
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if (EltVT.getSizeInBits() == 64) {
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VecSize = 2;
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}
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EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
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for (unsigned i = 0; i < NumElts; i += VecSize) {
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Value *SrcValue = Constant::getNullValue(
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PointerType::get(VecVT.getTypeForEVT(F->getContext()),
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llvm::ADDRESS_SPACE_PARAM));
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SDValue SrcAddr =
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DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
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DAG.getConstant(Ofst, getPointerTy()));
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SDValue P = DAG.getLoad(
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VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
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false, true,
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TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
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if (P.getNode())
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P.getNode()->setIROrder(idx + 1);
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for (unsigned j = 0; j < VecSize; ++j) {
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if (i + j >= NumElts)
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break;
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SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
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DAG.getIntPtrConstant(j));
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InVals.push_back(Elt);
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}
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Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
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InsIdx += VecSize;
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}
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}
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if (NumElts > 0)
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--InsIdx;
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continue;
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}
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// A plain scalar.
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EVT ObjectVT = getValueType(Ty);
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assert(ObjectVT == Ins[InsIdx].VT &&
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"Ins type did not match function type");
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// If ABI, load from the param symbol
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SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
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Value *srcValue = Constant::getNullValue(PointerType::get(
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ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
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SDValue p = DAG.getLoad(
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ObjectVT, dl, Root, Arg, MachinePointerInfo(srcValue), false, false,
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true,
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TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
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if (p.getNode())
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p.getNode()->setIROrder(idx + 1);
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InVals.push_back(p);
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continue;
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}
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// Param has ByVal attribute
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if (isABI || isKernel) {
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// Return MoveParam(param symbol).
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// Ideally, the param symbol can be returned directly,
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// but when SDNode builder decides to use it in a CopyToReg(),
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// machine instruction fails because TargetExternalSymbol
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// (not lowered) is target dependent, and CopyToReg assumes
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// the source is lowered.
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SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
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SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
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if (p.getNode())
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p.getNode()->setIROrder(idx + 1);
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if (isKernel)
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InVals.push_back(p);
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else {
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SDValue p2 = DAG.getNode(
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ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
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DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
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InVals.push_back(p2);
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}
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} else {
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// Have to move a set of param symbols to registers and
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// store them locally and return the local pointer in InVals
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const PointerType *elemPtrType = dyn_cast<PointerType>(argTypes[i]);
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assert(elemPtrType && "Byval parameter should be a pointer type");
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Type *elemType = elemPtrType->getElementType();
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// Compute the constituent parts
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SmallVector<EVT, 16> vtparts;
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SmallVector<uint64_t, 16> offsets;
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ComputeValueVTs(*this, elemType, vtparts, &offsets, 0);
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unsigned totalsize = 0;
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for (unsigned j = 0, je = vtparts.size(); j != je; ++j)
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totalsize += vtparts[j].getStoreSizeInBits();
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SDValue localcopy = DAG.getFrameIndex(
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MF.getFrameInfo()->CreateStackObject(totalsize / 8, 16, false),
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getPointerTy());
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unsigned sizesofar = 0;
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std::vector<SDValue> theChains;
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for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
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unsigned numElems = 1;
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if (vtparts[j].isVector())
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numElems = vtparts[j].getVectorNumElements();
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for (unsigned k = 0, ke = numElems; k != ke; ++k) {
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EVT tmpvt = vtparts[j];
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if (tmpvt.isVector())
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tmpvt = tmpvt.getVectorElementType();
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SDValue arg = DAG.getNode(NVPTXISD::MoveParam, dl, tmpvt,
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getParamSymbol(DAG, idx, tmpvt));
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SDValue addr =
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DAG.getNode(ISD::ADD, dl, getPointerTy(), localcopy,
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DAG.getConstant(sizesofar, getPointerTy()));
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theChains.push_back(DAG.getStore(
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Chain, dl, arg, addr, MachinePointerInfo(), false, false, 0));
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sizesofar += tmpvt.getStoreSizeInBits() / 8;
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++idx;
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}
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}
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--idx;
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &theChains[0],
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theChains.size());
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InVals.push_back(localcopy);
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// Return MoveParam(param symbol).
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// Ideally, the param symbol can be returned directly,
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// but when SDNode builder decides to use it in a CopyToReg(),
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// machine instruction fails because TargetExternalSymbol
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// (not lowered) is target dependent, and CopyToReg assumes
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// the source is lowered.
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EVT ObjectVT = getValueType(Ty);
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assert(ObjectVT == Ins[InsIdx].VT &&
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"Ins type did not match function type");
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SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
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SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
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if (p.getNode())
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p.getNode()->setIROrder(idx + 1);
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if (isKernel)
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InVals.push_back(p);
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else {
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SDValue p2 = DAG.getNode(
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ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
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DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
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InVals.push_back(p2);
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}
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}
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// Clang will check explicit VarArg and issue error if any. However, Clang
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// will let code with
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// implicit var arg like f() pass.
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// implicit var arg like f() pass. See bug 617733.
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// We treat this case as if the arg list is empty.
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//if (F.isVarArg()) {
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// if (F.isVarArg()) {
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// assert(0 && "VarArg not supported yet!");
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//}
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@ -1250,6 +1337,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
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return Chain;
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}
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SDValue NVPTXTargetLowering::LowerReturn(
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SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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@ -4,8 +4,7 @@
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define float @foo(<2 x float> %a) {
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; CHECK: .func (.param .b32 func_retval0) foo
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; CHECK: .param .align 8 .b8 foo_param_0[8]
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; CHECK: ld.param.f32 %f{{[0-9]+}}
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; CHECK: ld.param.f32 %f{{[0-9]+}}
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; CHECK: ld.param.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = fmul <2 x float> %a, %a
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%t2 = extractelement <2 x float> %t1, i32 0
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%t3 = extractelement <2 x float> %t1, i32 1
|
||||
@ -17,8 +16,7 @@ define float @foo(<2 x float> %a) {
|
||||
define float @bar(<4 x float> %a) {
|
||||
; CHECK: .func (.param .b32 func_retval0) bar
|
||||
; CHECK: .param .align 16 .b8 bar_param_0[16]
|
||||
; CHECK: ld.param.f32 %f{{[0-9]+}}
|
||||
; CHECK: ld.param.f32 %f{{[0-9]+}}
|
||||
; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
|
||||
%t1 = fmul <4 x float> %a, %a
|
||||
%t2 = extractelement <4 x float> %t1, i32 0
|
||||
%t3 = extractelement <4 x float> %t1, i32 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user