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Fixed a bug in the IT mask printing where T means the cond bit in the mask

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matches that of Firstcond[0] and E means otherwise.  The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing.  The disassembler also depends
on this arrangement.  This is similar to what's described in A2.5.2 ITSTATE.

Ran:

utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2

successfully.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98775 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-03-17 23:14:23 +00:00
parent 77bdc48eb6
commit b675e255d0
1 changed files with 5 additions and 3 deletions
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8
lib/Target/ARM/Thumb2ITBlockPass.cpp
View File

@ -78,14 +78,16 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
DebugLoc ndl = NMI->getDebugLoc();
unsigned NPredReg = 0;
ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
if (NCC == OCC) {
Mask |= (1 << Pos);
} else if (NCC != CC)
if (NCC == CC || NCC == OCC)
Mask |= (NCC & 1) << Pos;
else
break;
--Pos;
++MBBI;
}
Mask |= (1 << Pos);
// Tag along (firstcond[0] << 4) with the mask.
Mask |= (CC & 1) << 4;
MIB.addImm(Mask);
Modified = true;
++NumITs;