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Fixed a bug in the IT mask printing where T means the cond bit in the mask
matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also tagged in the Mask to facilitate Asm printing. The disassembler also depends on this arrangement. This is similar to what's described in A2.5.2 ITSTATE. Ran: utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2 successfully. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98775 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -78,14 +78,16 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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DebugLoc ndl = NMI->getDebugLoc();
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unsigned NPredReg = 0;
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ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
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if (NCC == OCC) {
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Mask |= (1 << Pos);
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} else if (NCC != CC)
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if (NCC == CC || NCC == OCC)
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Mask |= (NCC & 1) << Pos;
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else
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break;
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--Pos;
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++MBBI;
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}
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Mask |= (1 << Pos);
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// Tag along (firstcond[0] << 4) with the mask.
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Mask |= (CC & 1) << 4;
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MIB.addImm(Mask);
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Modified = true;
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++NumITs;
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