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Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can
do with nuw here, but sub and mul should be given similar treatment. Fixes PR9343 #15! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127463 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -429,6 +429,20 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
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KnownZero |= LHSKnownZero & Mask;
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KnownZero |= LHSKnownZero & Mask;
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KnownOne |= LHSKnownOne & Mask;
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KnownOne |= LHSKnownOne & Mask;
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}
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}
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// Are we still trying to solve for the sign bit?
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if (Mask.isNegative() && !KnownZero.isNegative() && !KnownOne.isNegative()){
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OverflowingBinaryOperator *OBO = cast<OverflowingBinaryOperator>(I);
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if (OBO->hasNoSignedWrap()) {
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// Adding two positive numbers can't wrap into negative ...
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if (LHSKnownZero.isNegative() && KnownZero2.isNegative())
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KnownZero |= APInt::getSignBit(BitWidth);
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// and adding two negative numbers can't wrap into positive.
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else if (LHSKnownOne.isNegative() && KnownOne2.isNegative())
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KnownOne |= APInt::getSignBit(BitWidth);
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}
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}
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return;
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return;
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}
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}
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case Instruction::SRem:
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case Instruction::SRem:
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@ -261,6 +261,16 @@ define i1 @srem1(i32 %X) {
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; CHECK: ret i1 false
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; CHECK: ret i1 false
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}
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}
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; PR9343 #15
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; CHECK: @srem2
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; CHECK: ret i1 false
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define i1 @srem2(i16 %X, i32 %Y) {
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%A = zext i16 %X to i32
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%B = add nsw i32 %A, 1
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%C = srem i32 %B, %Y
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%D = icmp slt i32 %C, 0
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ret i1 %D
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}
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define i1 @udiv1(i32 %X) {
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define i1 @udiv1(i32 %X) {
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; CHECK: @udiv1
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; CHECK: @udiv1
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%A = udiv i32 %X, 1000000
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%A = udiv i32 %X, 1000000
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