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Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,

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so I generalized the class for VTRN in the .td file to handle all 3 of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2009-08-08 06:13:25 +00:00
parent 64efd90f8c
commit b6ab51e829
2 changed files with 70 additions and 16 deletions
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33
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -1459,6 +1459,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
default: break;
case Intrinsic::arm_neon_vtrni:
case Intrinsic::arm_neon_vtrnf:
switch (VT.getSimpleVT()) {
default: return NULL;
case MVT::v8i8: Opc = ARM::VTRNd8; break;
@@ -1472,6 +1473,38 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
case Intrinsic::arm_neon_vuzpi:
case Intrinsic::arm_neon_vuzpf:
switch (VT.getSimpleVT()) {
default: return NULL;
case MVT::v8i8: Opc = ARM::VUZPd8; break;
case MVT::v4i16: Opc = ARM::VUZPd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VUZPd32; break;
case MVT::v16i8: Opc = ARM::VUZPq8; break;
case MVT::v8i16: Opc = ARM::VUZPq16; break;
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VUZPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
case Intrinsic::arm_neon_vzipi:
case Intrinsic::arm_neon_vzipf:
switch (VT.getSimpleVT()) {
default: return NULL;
case MVT::v8i8: Opc = ARM::VZIPd8; break;
case MVT::v4i16: Opc = ARM::VZIPd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VZIPd32; break;
case MVT::v16i8: Opc = ARM::VZIPq8; break;
case MVT::v8i16: Opc = ARM::VZIPq16; break;
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VZIPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
}
break;
}