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Add comments documenting the ARM datalayout string.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196850 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2013-12-10 00:37:37 +00:00
parent 8c087da028
commit b6c1f7e9f0
1 changed files with 12 additions and 0 deletions
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12
lib/Target/ARM/ARMTargetMachine.cpp
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@ -68,26 +68,38 @@ void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
void ARMTargetMachine::anchor() { } void ARMTargetMachine::anchor() { }
static std::string computeDataLayout(ARMSubtarget &ST) { static std::string computeDataLayout(ARMSubtarget &ST) {
// Little endian. Pointers are 32 bits and aligned to 32 bits.
std::string Ret = "e-p:32:32"; std::string Ret = "e-p:32:32";
// We have 64 bits floats and integers. The APCS ABI requires them to be
// aligned s them to 32 bits, others to 64 bits. We always try to align to
// 64 bits.
if (ST.isAPCS_ABI()) if (ST.isAPCS_ABI())
Ret += "-f64:32:64-i64:32:64"; Ret += "-f64:32:64-i64:32:64";
else else
Ret += "-f64:64:64-i64:64:64"; Ret += "-f64:64:64-i64:64:64";
// On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
// align to 32.
if (ST.isThumb()) if (ST.isThumb())
Ret += "-i16:16:32-i8:8:32-i1:8:32"; Ret += "-i16:16:32-i8:8:32-i1:8:32";
// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
// to 64. We always ty to give them natural alignment.
if (ST.isAPCS_ABI()) if (ST.isAPCS_ABI())
Ret += "-v128:32:128-v64:32:64"; Ret += "-v128:32:128-v64:32:64";
else else
Ret += "-v128:64:128-v64:64:64"; Ret += "-v128:64:128-v64:64:64";
// An aggregate of size 0 is ABI aligned to 0.
// FIXME: explain better what this means.
if (ST.isThumb()) if (ST.isThumb())
Ret += "-a:0:32"; Ret += "-a:0:32";
// Integer registers are 32 bits.
Ret += "-n32"; Ret += "-n32";
// The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
if (ST.isAAPCS_ABI()) if (ST.isAAPCS_ABI())
Ret += "-S64"; Ret += "-S64";
else else