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[PowerPC] Make use of VSX f64 <-> i64 conversion instructions

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When VSX is available, these instructions should be used in preference to the
older variants that only have access to the scalar floating-point registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204559 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2014-03-23 05:35:00 +00:00
parent fb51aac129
commit b6cbecd272
4 changed files with 111 additions and 6 deletions
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25
test/CodeGen/PowerPC/i32-to-float.ll
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@@ -1,6 +1,7 @@
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -29,6 +30,12 @@ entry:
; CHECK-A2: lfiwax [[REG:[0-9]+]],
; CHECK-A2: fcfids 1, [[REG]]
; CHECK-A2: blr
; CHECK-VSX: @foo
; CHECK-VSX: stw 3,
; CHECK-VSX: lfiwax [[REG:[0-9]+]],
; CHECK-VSX: fcfids 1, [[REG]]
; CHECK-VSX: blr
}
define double @goo(i32 %a) nounwind {
@@ -54,6 +61,12 @@ entry:
; CHECK-A2: lfiwax [[REG:[0-9]+]],
; CHECK-A2: fcfid 1, [[REG]]
; CHECK-A2: blr
; CHECK-VSX: @goo
; CHECK-VSX: stw 3,
; CHECK-VSX: lfiwax [[REG:[0-9]+]],
; CHECK-VSX: xscvsxddp 1, [[REG]]
; CHECK-VSX: blr
}
define float @foou(i32 %a) nounwind {
@@ -66,6 +79,12 @@ entry:
; CHECK-A2: lfiwzx [[REG:[0-9]+]],
; CHECK-A2: fcfidus 1, [[REG]]
; CHECK-A2: blr
; CHECK-VSX: @foou
; CHECK-VSX: stw 3,
; CHECK-VSX: lfiwzx [[REG:[0-9]+]],
; CHECK-VSX: fcfidus 1, [[REG]]
; CHECK-VSX: blr
}
define double @goou(i32 %a) nounwind {
@@ -78,5 +97,11 @@ entry:
; CHECK-A2: lfiwzx [[REG:[0-9]+]],
; CHECK-A2: fcfidu 1, [[REG]]
; CHECK-A2: blr
; CHECK-VSX: @goou
; CHECK-VSX: stw 3,
; CHECK-VSX: lfiwzx [[REG:[0-9]+]],
; CHECK-VSX: xscvuxddp 1, [[REG]]
; CHECK-VSX: blr
}