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Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
pseudos. rdar://problem/8614450 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131641 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -997,7 +997,8 @@ def : Pat<(extloadi64i32 addr:$src),
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// anyext. Define these to do an explicit zero-extend to
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// anyext. Define these to do an explicit zero-extend to
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// avoid partial-register updates.
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// avoid partial-register updates.
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def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
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def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
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(MOVZX32rr8 GR8 :$src), sub_16bit)>;
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def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
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def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
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// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
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// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
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@ -1164,9 +1165,9 @@ def : Pat<(and GR32:$src1, 0xff),
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>;
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// r & (2^8-1) ==> movz
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// r & (2^8-1) ==> movz
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def : Pat<(and GR16:$src1, 0xff),
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def : Pat<(and GR16:$src1, 0xff),
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(MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
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(EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
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GR16_ABCD)),
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(i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
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sub_8bit))>,
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sub_16bit)>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>;
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// r & (2^32-1) ==> movz
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// r & (2^32-1) ==> movz
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@ -1184,7 +1185,8 @@ def : Pat<(and GR32:$src1, 0xff),
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>;
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// r & (2^8-1) ==> movz
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// r & (2^8-1) ==> movz
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def : Pat<(and GR16:$src1, 0xff),
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def : Pat<(and GR16:$src1, 0xff),
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(MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
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(EXTRACT_SUBREG (MOVZX32rr8 (i8
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(EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>;
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@ -1196,10 +1198,11 @@ def : Pat<(sext_inreg GR32:$src, i8),
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GR32_ABCD)),
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GR32_ABCD)),
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sub_8bit))>,
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sub_8bit))>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>;
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def : Pat<(sext_inreg GR16:$src, i8),
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def : Pat<(sext_inreg GR16:$src, i8),
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(MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
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(EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
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GR16_ABCD)),
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(i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
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sub_8bit))>,
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sub_16bit)>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>;
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def : Pat<(sext_inreg GR64:$src, i32),
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def : Pat<(sext_inreg GR64:$src, i32),
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@ -1212,10 +1215,10 @@ def : Pat<(sext_inreg GR32:$src, i8),
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(MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
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(MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>;
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def : Pat<(sext_inreg GR16:$src, i8),
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def : Pat<(sext_inreg GR16:$src, i8),
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(MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
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(EXTRACT_SUBREG (MOVSX32rr8
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(EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>;
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// trunc patterns
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// trunc patterns
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def : Pat<(i16 (trunc GR32:$src)),
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def : Pat<(i16 (trunc GR32:$src)),
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(EXTRACT_SUBREG GR32:$src, sub_16bit)>;
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(EXTRACT_SUBREG GR32:$src, sub_16bit)>;
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@ -45,14 +45,12 @@ def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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// FIXME: Use a pat pattern or define a syntax here.
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let isCodeGenOnly=1 in {
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def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
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def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
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"", [(set GR16:$dst, (sext GR8:$src))]>, TB;
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (sext GR8:$src))]>, TB;
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def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
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def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
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"", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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}
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[(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
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def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sext GR8:$src))]>, TB;
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[(set GR32:$dst, (sext GR8:$src))]>, TB;
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@ -73,13 +71,12 @@ def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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// FIXME: Use a pat pattern or define a syntax here.
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let isCodeGenOnly=1 in {
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def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
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def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
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"", [(set GR16:$dst, (zext GR8:$src))]>, TB;
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (zext GR8:$src))]>, TB;
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def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
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def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
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"", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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}
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[(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
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def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zext GR8:$src))]>, TB;
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[(set GR32:$dst, (zext GR8:$src))]>, TB;
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@ -355,10 +355,6 @@ ReSimplify:
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assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
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assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
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"LEA has segment specified!");
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"LEA has segment specified!");
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break;
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break;
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case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
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case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
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case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
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case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
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case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
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case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
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case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
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case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
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case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
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case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
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