[PowerPC] Fix emitting instruction pairs on LE

My patch r204634 to emit instructions in little-endian format failed to
handle those special cases where we emit a pair of instructions from a
single LLVM MC instructions (like the bl; nop pairs used to implement
the call sequence).

In those cases, we still need to emit the "first" instruction (the one
in the more significant word) first, on both big and little endian,
and not swap them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211171 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2014-06-18 15:37:07 +00:00
parent 3fbbe94b93
commit b7074b8c2d

View File

@ -102,17 +102,45 @@ public:
// Output the constant in big/little endian byte order.
unsigned Size = Desc.getSize();
if (IsLittleEndian) {
for (unsigned i = 0; i != Size; ++i) {
OS << (char)Bits;
Bits >>= 8;
switch (Size) {
case 4:
if (IsLittleEndian) {
OS << (char)(Bits);
OS << (char)(Bits >> 8);
OS << (char)(Bits >> 16);
OS << (char)(Bits >> 24);
} else {
OS << (char)(Bits >> 24);
OS << (char)(Bits >> 16);
OS << (char)(Bits >> 8);
OS << (char)(Bits);
}
} else {
int ShiftValue = (Size * 8) - 8;
for (unsigned i = 0; i != Size; ++i) {
OS << (char)(Bits >> ShiftValue);
Bits <<= 8;
break;
case 8:
// If we emit a pair of instructions, the first one is
// always in the top 32 bits, even on little-endian.
if (IsLittleEndian) {
OS << (char)(Bits >> 32);
OS << (char)(Bits >> 40);
OS << (char)(Bits >> 48);
OS << (char)(Bits >> 56);
OS << (char)(Bits);
OS << (char)(Bits >> 8);
OS << (char)(Bits >> 16);
OS << (char)(Bits >> 24);
} else {
OS << (char)(Bits >> 56);
OS << (char)(Bits >> 48);
OS << (char)(Bits >> 40);
OS << (char)(Bits >> 32);
OS << (char)(Bits >> 24);
OS << (char)(Bits >> 16);
OS << (char)(Bits >> 8);
OS << (char)(Bits);
}
break;
default:
llvm_unreachable ("Invalid instruction size");
}
++MCNumEmitted; // Keep track of the # of mi's emitted.