mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-28 06:32:09 +00:00
* Implement rudimentary output of the constant pool
* Implement support for MRMS?m instructions * Add Arg64 support * Add support for frame indexes and constant pool indexes * git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5225 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
e831b6b802
commit
b708944fc2
@ -8,21 +8,24 @@
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/Constant.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "Support/Statistic.h"
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namespace {
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struct Printer : public MachineFunctionPass {
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std::ostream &O;
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Printer(std::ostream &o) : O(o) {}
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unsigned ConstIdx;
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Printer(std::ostream &o) : O(o), ConstIdx(0) {}
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virtual const char *getPassName() const {
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return "X86 Assembly Printer";
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}
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void printConstantPool(MachineConstantPool *MCP, const TargetData &TD);
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bool runOnMachineFunction(MachineFunction &F);
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};
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}
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@ -36,6 +39,21 @@ Pass *createX86CodePrinterPass(std::ostream &O) {
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}
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// printConstantPool - Print out any constants which have been spilled to
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// memory...
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void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
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const std::vector<Constant*> &CP = MCP->getConstants();
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if (CP.empty()) return;
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for (unsigned i = 0, e = CP.size(); i != e; ++i) {
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O << "\t.section .rodata\n";
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O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n";
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O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n";
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O << "\t*Constant output not implemented yet!*\n\n";
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}
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ConstIdx += CP.size(); // Don't recycle constant pool index numbers
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}
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/// runOnFunction - This uses the X86InstructionInfo::print method
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/// to print assembly for each instruction.
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bool Printer::runOnMachineFunction(MachineFunction &MF) {
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@ -43,7 +61,12 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) {
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const TargetMachine &TM = MF.getTarget();
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const MachineInstrInfo &MII = TM.getInstrInfo();
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// Print out constants referenced by the function
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printConstantPool(MF.getConstantPool(), TM.getTargetData());
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// Print out labels for the function.
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O << "\t.text\n";
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O << "\t.align 16\n";
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O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
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O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
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O << MF.getFunction()->getName() << ":\n";
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@ -72,6 +95,8 @@ static bool isScale(const MachineOperand &MO) {
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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if (MI->getOperand(Op).isConstantPoolIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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@ -85,6 +110,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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@ -99,6 +125,12 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
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case MachineOperand::MO_PCRelativeDisp:
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O << "<" << MO.getVRegValue()->getName() << ">";
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return;
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case MachineOperand::MO_GlobalAddress:
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O << "<" << MO.getGlobal()->getName() << ">";
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << "<" << MO.getSymbolName() << ">";
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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@ -110,6 +142,7 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
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case X86II::Arg8: return "BYTE PTR";
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case X86II::Arg16: return "WORD PTR";
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case X86II::Arg32: return "DWORD PTR";
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case X86II::Arg64: return "QWORD PTR";
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case X86II::ArgF32: return "DWORD PTR";
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case X86II::ArgF64: return "QWORD PTR";
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case X86II::ArgF80: return "XWORD PTR";
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@ -119,6 +152,21 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
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static void printMemReference(std::ostream &O, const MachineInstr *MI,
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unsigned Op, const MRegisterInfo &RI) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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} else if (MI->getOperand(Op).isConstantPoolIndex()) {
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O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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}
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const MachineOperand &BaseReg = MI->getOperand(Op);
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int ScaleVal = MI->getOperand(Op+1).getImmedValue();
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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@ -194,9 +242,13 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// The accepted forms of Raw instructions are:
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// 1. nop - No operand required
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// 2. jmp foo - PC relative displacement operand
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// 3. call bar - GlobalAddress Operand or External Symbol Operand
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//
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assert(MI->getNumOperands() == 0 ||
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(MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
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(MI->getNumOperands() == 1 &&
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(MI->getOperand(0).isPCRelativeDisp() ||
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MI->getOperand(0).isGlobalAddress() ||
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MI->getOperand(0).isExternalSymbol())) &&
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"Illegal raw instruction!");
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O << getName(MI->getOpcode()) << " ";
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@ -220,14 +272,20 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(1).getVRegValueOrNull() ||
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MI->getOperand(1).isImmediate() ||
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MI->getOperand(1).isRegister()))) &&
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MI->getOperand(1).isRegister() ||
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MI->getOperand(1).isGlobalAddress() ||
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MI->getOperand(1).isExternalSymbol()))) &&
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"Illegal form for AddRegFrm instruction!");
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unsigned Reg = MI->getOperand(0).getReg();
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) {
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if (MI->getNumOperands() == 2 &&
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(!MI->getOperand(1).isRegister() ||
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MI->getOperand(1).getVRegValueOrNull() ||
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MI->getOperand(1).isGlobalAddress() ||
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MI->getOperand(1).isExternalSymbol())) {
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O << ", ";
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printOp(O, MI->getOperand(1), RI);
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}
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@ -235,29 +293,36 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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return;
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}
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case X86II::MRMDestReg: {
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// There are two acceptable forms of MRMDestReg instructions, those with 3
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// and 2 operands:
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// There are two acceptable forms of MRMDestReg instructions, those with 2,
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// 3 and 4 operands:
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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// 3 Operands: in this form, the first two registers (the destination, and
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// the first operand) should be the same, post register allocation. The 3rd
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// operand is an additional input. This should be for things like add
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// instructions.
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//
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// 2 Operands: this is for things like mov that do not read a second input
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// 4 Operands: This form is for instructions which are 3 operands forms, but
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// have a constant argument as well.
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//
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bool isTwoAddr = isTwoAddrInstr(Opcode);
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
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MI->getOperand(MI->getNumOperands()-1).isRegister()
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(MI->getNumOperands() == 2 ||
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(isTwoAddr && MI->getOperand(1).isRegister() &&
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MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
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(MI->getNumOperands() == 3 ||
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(MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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printOp(O, MI->getOperand(1+isTwoAddr), RI);
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if (MI->getNumOperands() == 4) {
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O << ", ";
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printOp(O, MI->getOperand(3), RI);
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}
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O << "\n";
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return;
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}
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@ -269,7 +334,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
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O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
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O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
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printMemReference(O, MI, 0, RI);
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O << ", ";
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printOp(O, MI->getOperand(4), RI);
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@ -291,7 +356,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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MI->getOperand(1).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
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&& "Bad format for MRMDestReg!");
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&& "Bad format for MRMSrcReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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@ -319,7 +384,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", " << sizePtr (Desc) << " ";
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O << ", " << sizePtr(Desc) << " ";
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printMemReference(O, MI, MI->getNumOperands()-4, RI);
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O << "\n";
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return;
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@ -359,7 +424,33 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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return;
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}
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case X86II::MRMS0m: case X86II::MRMS1m:
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case X86II::MRMS2m: case X86II::MRMS3m:
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case X86II::MRMS4m: case X86II::MRMS5m:
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case X86II::MRMS6m: case X86II::MRMS7m: {
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// In this form, the following are valid formats:
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// 1. sete [m]
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// 2. cmp [m], immediate
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// 2. shl [m], rinput <implicit CL or 1>
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// 3. sbb [m], immediate
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//
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assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
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isMem(MI, 0) && "Bad MRMSxM format!");
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assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
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"Bad MRMSxM format!");
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O << getName(MI->getOpCode()) << " ";
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O << sizePtr(Desc) << " ";
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printMemReference(O, MI, 0, RI);
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if (MI->getNumOperands() == 5) {
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O << ", ";
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printOp(O, MI->getOperand(4), RI);
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}
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O << "\n";
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return;
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}
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default:
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O << "\t\t\t-"; MI->print(O, TM); break;
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O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
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}
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}
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@ -8,21 +8,24 @@
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/Constant.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "Support/Statistic.h"
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namespace {
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struct Printer : public MachineFunctionPass {
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std::ostream &O;
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Printer(std::ostream &o) : O(o) {}
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unsigned ConstIdx;
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Printer(std::ostream &o) : O(o), ConstIdx(0) {}
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virtual const char *getPassName() const {
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return "X86 Assembly Printer";
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}
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void printConstantPool(MachineConstantPool *MCP, const TargetData &TD);
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bool runOnMachineFunction(MachineFunction &F);
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};
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}
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@ -36,6 +39,21 @@ Pass *createX86CodePrinterPass(std::ostream &O) {
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}
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// printConstantPool - Print out any constants which have been spilled to
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// memory...
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void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
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const std::vector<Constant*> &CP = MCP->getConstants();
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if (CP.empty()) return;
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for (unsigned i = 0, e = CP.size(); i != e; ++i) {
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O << "\t.section .rodata\n";
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O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n";
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O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n";
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O << "\t*Constant output not implemented yet!*\n\n";
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}
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ConstIdx += CP.size(); // Don't recycle constant pool index numbers
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}
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/// runOnFunction - This uses the X86InstructionInfo::print method
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/// to print assembly for each instruction.
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bool Printer::runOnMachineFunction(MachineFunction &MF) {
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@ -43,7 +61,12 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) {
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const TargetMachine &TM = MF.getTarget();
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const MachineInstrInfo &MII = TM.getInstrInfo();
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// Print out constants referenced by the function
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printConstantPool(MF.getConstantPool(), TM.getTargetData());
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// Print out labels for the function.
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O << "\t.text\n";
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O << "\t.align 16\n";
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O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
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O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
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O << MF.getFunction()->getName() << ":\n";
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@ -72,6 +95,8 @@ static bool isScale(const MachineOperand &MO) {
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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if (MI->getOperand(Op).isConstantPoolIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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@ -85,6 +110,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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@ -99,6 +125,12 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
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case MachineOperand::MO_PCRelativeDisp:
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O << "<" << MO.getVRegValue()->getName() << ">";
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return;
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case MachineOperand::MO_GlobalAddress:
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O << "<" << MO.getGlobal()->getName() << ">";
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << "<" << MO.getSymbolName() << ">";
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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@ -110,6 +142,7 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
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case X86II::Arg8: return "BYTE PTR";
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case X86II::Arg16: return "WORD PTR";
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case X86II::Arg32: return "DWORD PTR";
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case X86II::Arg64: return "QWORD PTR";
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case X86II::ArgF32: return "DWORD PTR";
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case X86II::ArgF64: return "QWORD PTR";
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case X86II::ArgF80: return "XWORD PTR";
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@ -119,6 +152,21 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
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static void printMemReference(std::ostream &O, const MachineInstr *MI,
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unsigned Op, const MRegisterInfo &RI) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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} else if (MI->getOperand(Op).isConstantPoolIndex()) {
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O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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}
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const MachineOperand &BaseReg = MI->getOperand(Op);
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int ScaleVal = MI->getOperand(Op+1).getImmedValue();
|
||||
const MachineOperand &IndexReg = MI->getOperand(Op+2);
|
||||
@ -194,9 +242,13 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
// The accepted forms of Raw instructions are:
|
||||
// 1. nop - No operand required
|
||||
// 2. jmp foo - PC relative displacement operand
|
||||
// 3. call bar - GlobalAddress Operand or External Symbol Operand
|
||||
//
|
||||
assert(MI->getNumOperands() == 0 ||
|
||||
(MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
|
||||
(MI->getNumOperands() == 1 &&
|
||||
(MI->getOperand(0).isPCRelativeDisp() ||
|
||||
MI->getOperand(0).isGlobalAddress() ||
|
||||
MI->getOperand(0).isExternalSymbol())) &&
|
||||
"Illegal raw instruction!");
|
||||
O << getName(MI->getOpcode()) << " ";
|
||||
|
||||
@ -220,14 +272,20 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
(MI->getNumOperands() == 2 &&
|
||||
(MI->getOperand(1).getVRegValueOrNull() ||
|
||||
MI->getOperand(1).isImmediate() ||
|
||||
MI->getOperand(1).isRegister()))) &&
|
||||
MI->getOperand(1).isRegister() ||
|
||||
MI->getOperand(1).isGlobalAddress() ||
|
||||
MI->getOperand(1).isExternalSymbol()))) &&
|
||||
"Illegal form for AddRegFrm instruction!");
|
||||
|
||||
unsigned Reg = MI->getOperand(0).getReg();
|
||||
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) {
|
||||
if (MI->getNumOperands() == 2 &&
|
||||
(!MI->getOperand(1).isRegister() ||
|
||||
MI->getOperand(1).getVRegValueOrNull() ||
|
||||
MI->getOperand(1).isGlobalAddress() ||
|
||||
MI->getOperand(1).isExternalSymbol())) {
|
||||
O << ", ";
|
||||
printOp(O, MI->getOperand(1), RI);
|
||||
}
|
||||
@ -235,29 +293,36 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
return;
|
||||
}
|
||||
case X86II::MRMDestReg: {
|
||||
// There are two acceptable forms of MRMDestReg instructions, those with 3
|
||||
// and 2 operands:
|
||||
// There are two acceptable forms of MRMDestReg instructions, those with 2,
|
||||
// 3 and 4 operands:
|
||||
//
|
||||
// 2 Operands: this is for things like mov that do not read a second input
|
||||
//
|
||||
// 3 Operands: in this form, the first two registers (the destination, and
|
||||
// the first operand) should be the same, post register allocation. The 3rd
|
||||
// operand is an additional input. This should be for things like add
|
||||
// instructions.
|
||||
//
|
||||
// 2 Operands: this is for things like mov that do not read a second input
|
||||
// 4 Operands: This form is for instructions which are 3 operands forms, but
|
||||
// have a constant argument as well.
|
||||
//
|
||||
bool isTwoAddr = isTwoAddrInstr(Opcode);
|
||||
assert(MI->getOperand(0).isRegister() &&
|
||||
(MI->getNumOperands() == 2 ||
|
||||
(MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
|
||||
MI->getOperand(MI->getNumOperands()-1).isRegister()
|
||||
(MI->getNumOperands() == 2 ||
|
||||
(isTwoAddr && MI->getOperand(1).isRegister() &&
|
||||
MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
|
||||
(MI->getNumOperands() == 3 ||
|
||||
(MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
|
||||
&& "Bad format for MRMDestReg!");
|
||||
if (MI->getNumOperands() == 3 &&
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", ";
|
||||
printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
|
||||
printOp(O, MI->getOperand(1+isTwoAddr), RI);
|
||||
if (MI->getNumOperands() == 4) {
|
||||
O << ", ";
|
||||
printOp(O, MI->getOperand(3), RI);
|
||||
}
|
||||
O << "\n";
|
||||
return;
|
||||
}
|
||||
@ -269,7 +334,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
|
||||
MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
|
||||
|
||||
O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
|
||||
O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
|
||||
printMemReference(O, MI, 0, RI);
|
||||
O << ", ";
|
||||
printOp(O, MI->getOperand(4), RI);
|
||||
@ -291,7 +356,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
MI->getOperand(1).isRegister() &&
|
||||
(MI->getNumOperands() == 2 ||
|
||||
(MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
|
||||
&& "Bad format for MRMDestReg!");
|
||||
&& "Bad format for MRMSrcReg!");
|
||||
if (MI->getNumOperands() == 3 &&
|
||||
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
||||
O << "**";
|
||||
@ -319,7 +384,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
printOp(O, MI->getOperand(0), RI);
|
||||
O << ", " << sizePtr (Desc) << " ";
|
||||
O << ", " << sizePtr(Desc) << " ";
|
||||
printMemReference(O, MI, MI->getNumOperands()-4, RI);
|
||||
O << "\n";
|
||||
return;
|
||||
@ -359,7 +424,33 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
|
||||
return;
|
||||
}
|
||||
|
||||
case X86II::MRMS0m: case X86II::MRMS1m:
|
||||
case X86II::MRMS2m: case X86II::MRMS3m:
|
||||
case X86II::MRMS4m: case X86II::MRMS5m:
|
||||
case X86II::MRMS6m: case X86II::MRMS7m: {
|
||||
// In this form, the following are valid formats:
|
||||
// 1. sete [m]
|
||||
// 2. cmp [m], immediate
|
||||
// 2. shl [m], rinput <implicit CL or 1>
|
||||
// 3. sbb [m], immediate
|
||||
//
|
||||
assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
|
||||
isMem(MI, 0) && "Bad MRMSxM format!");
|
||||
assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
|
||||
"Bad MRMSxM format!");
|
||||
|
||||
O << getName(MI->getOpCode()) << " ";
|
||||
O << sizePtr(Desc) << " ";
|
||||
printMemReference(O, MI, 0, RI);
|
||||
if (MI->getNumOperands() == 5) {
|
||||
O << ", ";
|
||||
printOp(O, MI->getOperand(4), RI);
|
||||
}
|
||||
O << "\n";
|
||||
return;
|
||||
}
|
||||
|
||||
default:
|
||||
O << "\t\t\t-"; MI->print(O, TM); break;
|
||||
O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user