From b70a05a871a9ce44231a5f6308271f333c4ad110 Mon Sep 17 00:00:00 2001 From: Jin-Gu Kang Date: Thu, 3 Oct 2013 15:58:48 +0000 Subject: [PATCH] Added checking code whehter target supports specific dag combining about rotate or not. The corresponding dag patterns are as following: "DAGCombier::MatchRotate" function in DAGCombiner.cpp Pattern1 // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotr x, (sub 32, y))) pattern2 // fold (or (shl (*ext x), (*ext (sub 32, y))), // (srl (*ext x), (*ext y))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext (sub 32, y))), // (srl (*ext x), (*ext y))) -> // (*ext (rotr x, (sub 32, y))) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191905 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 30 +++++++++++++++--------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f9458925885..5dd4376de7b 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3415,12 +3415,16 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) { // (*ext (rotr x, (sub 32, y))) SDValue LArgExtOp0 = LHSShiftArg.getOperand(0); EVT LArgVT = LArgExtOp0.getValueType(); - if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) { - SDValue V = - DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, LArgVT, - LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt); - return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode(); - } + bool HasROTRWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTR, LArgVT); + bool HasROTLWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTL, LArgVT); + if (HasROTRWithLArg || HasROTLWithLArg) { + if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) { + SDValue V = + DAG.getNode(HasROTLWithLArg ? ISD::ROTL : ISD::ROTR, DL, LArgVT, + LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt); + return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode(); + } + } } } } else if (LExtOp0.getOpcode() == ISD::SUB && @@ -3444,11 +3448,15 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) { // (*ext (rotr x, (sub 32, y))) SDValue RArgExtOp0 = RHSShiftArg.getOperand(0); EVT RArgVT = RArgExtOp0.getValueType(); - if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) { - SDValue V = - DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, RArgVT, - RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt); - return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode(); + bool HasROTRWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTR, RArgVT); + bool HasROTLWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTL, RArgVT); + if (HasROTRWithRArg || HasROTLWithRArg) { + if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) { + SDValue V = + DAG.getNode(HasROTRWithRArg ? ISD::ROTR : ISD::ROTL, DL, RArgVT, + RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt); + return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode(); + } } } }