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Implement Transforms/InstCombine/shift-sra.ll:test0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30450 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1089,6 +1089,26 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, uint64_t DemandedMask,
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}
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break;
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case Instruction::Shr:
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// If this is an arithmetic shift right and only the low-bit is set, we can
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// always convert this into a logical shr, even if the shift amount is
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// variable. The low bit of the shift cannot be an input sign bit unless
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// the shift amount is >= the size of the datatype, which is undefined.
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if (DemandedMask == 1 && I->getType()->isSigned()) {
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// Convert the input to unsigned.
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Instruction *NewVal = new CastInst(I->getOperand(0),
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I->getType()->getUnsignedVersion(),
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I->getOperand(0)->getName());
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InsertNewInstBefore(NewVal, *I);
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// Perform the unsigned shift right.
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NewVal = new ShiftInst(Instruction::Shr, NewVal, I->getOperand(1),
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I->getName());
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InsertNewInstBefore(NewVal, *I);
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// Then cast that to the destination type.
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NewVal = new CastInst(NewVal, I->getType(), I->getName());
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InsertNewInstBefore(NewVal, *I);
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return UpdateValueUsesWith(I, NewVal);
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}
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if (ConstantUInt *SA = dyn_cast<ConstantUInt>(I->getOperand(1))) {
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unsigned ShAmt = SA->getValue();
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