From b74bb1a7a471a77e793d90de158aa4bbc67fe94d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 24 Jul 2009 00:53:56 +0000 Subject: [PATCH] FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseInstrInfo.cpp | 56 ++++++++++++-------------- lib/Target/ARM/ARMBaseInstrInfo.h | 10 +---- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 6 +-- lib/Target/ARM/ARMInstrInfo.cpp | 8 ---- lib/Target/ARM/Thumb1InstrInfo.cpp | 8 ---- lib/Target/ARM/Thumb2InstrInfo.cpp | 8 ---- 6 files changed, 29 insertions(+), 67 deletions(-) diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 6dbd9e50fd7..a2d326d6520 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -488,10 +488,10 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, SrcSubIdx = DstSubIdx = 0; // No sub-registers. unsigned oc = MI.getOpcode(); - if ((oc == getOpcode(ARMII::FCPYS)) || - (oc == getOpcode(ARMII::FCPYD)) || - (oc == getOpcode(ARMII::VMOVD)) || - (oc == getOpcode(ARMII::VMOVQ))) { + if (oc == ARM::FCPYS || + oc == ARM::FCPYD || + oc == ARM::VMOVD || + oc == ARM::VMOVQ) { SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; @@ -531,8 +531,7 @@ ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, return MI->getOperand(0).getReg(); } } - else if ((oc == getOpcode(ARMII::FLDD)) || - (oc == getOpcode(ARMII::FLDS))) { + else if (oc == ARM::FLDD || oc == ARM::FLDS) { if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) { @@ -566,8 +565,7 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, return MI->getOperand(0).getReg(); } } - else if ((oc == getOpcode(ARMII::FSTD)) || - (oc == getOpcode(ARMII::FSTS))) { + else if (oc == ARM::FSTD || oc == ARM::FSTS) { if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) { @@ -597,13 +595,13 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), DestReg).addReg(SrcReg))); else if (DestRC == ARM::SPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYS)), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) .addReg(SrcReg)); else if (DestRC == ARM::DPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYD)), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) .addReg(SrcReg)); else if (DestRC == ARM::QPRRegisterClass) - BuildMI(MBB, I, DL, get(getOpcode(ARMII::VMOVQ)), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); else return false; @@ -622,12 +620,12 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FSTD))) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FSTS))) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0)); } @@ -647,10 +645,10 @@ ARMBaseInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else Opc = getOpcode(ARMII::STRrr); } else if (RC == ARM::DPRRegisterClass) { - Opc = getOpcode(ARMII::FSTD); + Opc = ARM::FSTD; } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - Opc = getOpcode(ARMII::FSTS); + Opc = ARM::FSTS; } MachineInstrBuilder MIB = @@ -673,11 +671,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDRrr)), DestReg) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FLDD)), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FLDS)), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) .addFrameIndex(FI).addImm(0)); } } @@ -695,10 +693,10 @@ loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else Opc = getOpcode(ARMII::LDRrr); } else if (RC == ARM::DPRRegisterClass) { - Opc = getOpcode(ARMII::FLDD); + Opc = ARM::FLDD; } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - Opc = getOpcode(ARMII::FLDS); + Opc = ARM::FLDS; } MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); @@ -742,14 +740,14 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, } } } - else if (Opc == getOpcode(ARMII::FCPYS)) { + else if (Opc == ARM::FCPYS) { unsigned Pred = MI->getOperand(2).getImm(); unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); bool isUndef = MI->getOperand(1).isUndef(); - NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FSTS))) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) .addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); @@ -757,7 +755,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); bool isUndef = MI->getOperand(0).isUndef(); - NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FLDS))) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | @@ -765,21 +763,21 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } } - else if (Opc == getOpcode(ARMII::FCPYD)) { + else if (Opc == ARM::FCPYD) { unsigned Pred = MI->getOperand(2).getImm(); unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); bool isUndef = MI->getOperand(1).isUndef(); - NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FSTD))) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); bool isUndef = MI->getOperand(0).isUndef(); - NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FLDD))) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | @@ -808,13 +806,9 @@ ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, if (Opc == getOpcode(ARMII::MOVr)) { // If it is updating CPSR, then it cannot be folded. return MI->getOperand(4).getReg() != ARM::CPSR; - } - else if ((Opc == getOpcode(ARMII::FCPYS)) || - (Opc == getOpcode(ARMII::FCPYD))) { + } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { return true; - } - else if ((Opc == getOpcode(ARMII::VMOVD)) || - (Opc == getOpcode(ARMII::VMOVQ))) { + } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) { return false; // FIXME } diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index 6445cc118dd..eda7ab76eed 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -171,12 +171,6 @@ namespace ARMII { BR_JTm, BR_JTadd, BX_RET, - FCPYS, - FCPYD, - FLDD, - FLDS, - FSTD, - FSTS, LDRrr, LDRri, MOVr, @@ -184,9 +178,7 @@ namespace ARMII { STRri, SUBri, SUBrs, - SUBrr, - VMOVD, - VMOVQ + SUBrr }; } diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 5591de1b45f..d93c4edb4e1 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1335,7 +1335,7 @@ emitPrologue(MachineFunction &MF) const { NumBytes = DPRCSOffset; if (NumBytes) { // Insert it after all the callee-save spills. - movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FSTD), 0, 3, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI); emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes); } @@ -1359,7 +1359,7 @@ static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { static bool isCSRestore(MachineInstr *MI, const ARMBaseInstrInfo &TII, const unsigned *CSRegs) { - return ((MI->getOpcode() == (int)TII.getOpcode(ARMII::FLDD) || + return ((MI->getOpcode() == (int)ARM::FLDD || MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRrr) || MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRri)) && MI->getOperand(1).isFI() && @@ -1422,7 +1422,7 @@ emitEpilogue(MachineFunction &MF, } // Move SP to start of integer callee save spill area 2. - movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FLDD), 0, 3, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI); emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize()); // Move SP to start of integer callee save spill area 1. diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index ff4474f9080..56a6b0b1d8c 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -74,12 +74,6 @@ getOpcode(ARMII::Op Op) const { case ARMII::BR_JTm: return ARM::BR_JTm; case ARMII::BR_JTadd: return ARM::BR_JTadd; case ARMII::BX_RET: return ARM::BX_RET; - case ARMII::FCPYS: return ARM::FCPYS; - case ARMII::FCPYD: return ARM::FCPYD; - case ARMII::FLDD: return ARM::FLDD; - case ARMII::FLDS: return ARM::FLDS; - case ARMII::FSTD: return ARM::FSTD; - case ARMII::FSTS: return ARM::FSTS; case ARMII::LDRrr: return ARM::LDR; case ARMII::LDRri: return 0; case ARMII::MOVr: return ARM::MOVr; @@ -88,8 +82,6 @@ getOpcode(ARMII::Op Op) const { case ARMII::SUBri: return ARM::SUBri; case ARMII::SUBrs: return ARM::SUBrs; case ARMII::SUBrr: return ARM::SUBrr; - case ARMII::VMOVD: return ARM::VMOVD; - case ARMII::VMOVQ: return ARM::VMOVQ; default: break; } diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp index 1593c87b002..81dd3df87a7 100644 --- a/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -41,12 +41,6 @@ unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const { case ARMII::BR_JTm: return 0; case ARMII::BR_JTadd: return 0; case ARMII::BX_RET: return ARM::tBX_RET; - case ARMII::FCPYS: return 0; - case ARMII::FCPYD: return 0; - case ARMII::FLDD: return 0; - case ARMII::FLDS: return 0; - case ARMII::FSTD: return 0; - case ARMII::FSTS: return 0; case ARMII::LDRrr: return ARM::tLDR; case ARMII::LDRri: return 0; case ARMII::MOVr: return ARM::tMOVr; @@ -55,8 +49,6 @@ unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const { case ARMII::SUBri: return ARM::tSUBi8; case ARMII::SUBrs: return 0; case ARMII::SUBrr: return ARM::tSUBrr; - case ARMII::VMOVD: return 0; - case ARMII::VMOVQ: return 0; default: break; } diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 91a1dcbf436..4202b0151bf 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -42,12 +42,6 @@ unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const { case ARMII::BR_JTm: return ARM::t2BR_JTm; case ARMII::BR_JTadd: return ARM::t2BR_JTadd; case ARMII::BX_RET: return ARM::tBX_RET; - case ARMII::FCPYS: return ARM::FCPYS; - case ARMII::FCPYD: return ARM::FCPYD; - case ARMII::FLDD: return ARM::FLDD; - case ARMII::FLDS: return ARM::FLDS; - case ARMII::FSTD: return ARM::FSTD; - case ARMII::FSTS: return ARM::FSTS; case ARMII::LDRrr: return ARM::t2LDRs; case ARMII::LDRri: return ARM::t2LDRi12; case ARMII::MOVr: return ARM::t2MOVr; @@ -56,8 +50,6 @@ unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const { case ARMII::SUBri: return ARM::t2SUBri; case ARMII::SUBrs: return ARM::t2SUBrs; case ARMII::SUBrr: return ARM::t2SUBrr; - case ARMII::VMOVD: return ARM::VMOVD; - case ARMII::VMOVQ: return ARM::VMOVQ; default: break; }