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Propagate debug loc info in SimplifyBinOpWithSameOpcodeHands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63411 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1731,11 +1731,11 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
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if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
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N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
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N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
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SDValue ORNode = DAG.getNode(N->getOpcode(),
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N0.getOperand(0).getValueType(),
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N0.getOperand(0), N1.getOperand(0));
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SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
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N0.getOperand(0).getValueType(),
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N0.getOperand(0), N1.getOperand(0));
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AddToWorkList(ORNode.getNode());
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return DAG.getNode(N0.getOpcode(), VT, ORNode);
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return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
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}
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// For each of OP in SHL/SRL/SRA/AND...
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@ -1745,11 +1745,12 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
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if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
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N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
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N0.getOperand(1) == N1.getOperand(1)) {
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SDValue ORNode = DAG.getNode(N->getOpcode(),
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N0.getOperand(0).getValueType(),
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N0.getOperand(0), N1.getOperand(0));
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SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
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N0.getOperand(0).getValueType(),
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N0.getOperand(0), N1.getOperand(0));
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AddToWorkList(ORNode.getNode());
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return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
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return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
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ORNode, N0.getOperand(1));
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}
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return SDValue();
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