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Use multiclass for the store instructions with MEMri operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168983 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
65502aa5fd
commit
b76c710aab
@ -1634,12 +1634,6 @@ def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
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/// last operand.
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/// last operand.
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///
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///
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// Store doubleword.
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// Store doubleword.
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let isPredicable = 1 in
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def STrid : STInst<(outs),
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(ins MEMri:$addr, DoubleRegs:$src1),
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"memd($addr) = $src1",
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[(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr)]>;
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// Indexed store double word.
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// Indexed store double word.
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let AddedComplexity = 10, isPredicable = 1 in
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let AddedComplexity = 10, isPredicable = 1 in
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def STrid_indexed : STInst<(outs),
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def STrid_indexed : STInst<(outs),
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@ -1673,22 +1667,6 @@ def POST_STdri : STInstPI<(outs IntRegs:$dst),
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// Store doubleword conditionally.
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// Store doubleword conditionally.
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// if ([!]Pv) memd(Rs+#u6:3)=Rtt
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// if ([!]Pv) memd(Rs+#u6:3)=Rtt
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// if (Pv) memd(Rs+#u6:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrid_cPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
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"if ($src1) memd($addr) = $src2",
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[]>;
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// if (!Pv) memd(Rs+#u6:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrid_cNotPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
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"if (!$src1) memd($addr) = $src2",
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[]>;
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// if (Pv) memd(Rs+#u6:3)=Rtt
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// if (Pv) memd(Rs+#u6:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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isPredicated = 1 in
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@ -1728,15 +1706,73 @@ def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
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[],
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[],
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"$src3 = $dst">;
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"$src3 = $dst">;
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//===----------------------------------------------------------------------===//
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// multiclass for the store instructions with MEMri operand.
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//===----------------------------------------------------------------------===//
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multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($addr) = $src2",
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[]>;
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}
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multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
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// Predicate new
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let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
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defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
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}
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}
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let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
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multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
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bits<5> ImmBits, bits<5> PredImmBits> {
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let CextOpcode = CextOp, BaseOpcode = CextOp in {
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let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
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isPredicable = 1 in
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def #NAME# : STInst2<(outs),
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(ins MEMri:$addr, RC:$src),
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#mnemonic#"($addr) = $src",
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[]>;
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let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
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isPredicated = 1 in {
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defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
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defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
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}
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}
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}
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let addrMode = BaseImmOffset, isMEMri = "true" in {
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defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
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defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
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defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
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let isNVStorable = 0 in
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defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
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}
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def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
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(STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
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def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
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(STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
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def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
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(STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
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def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
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(STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
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// Store byte.
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// Store byte.
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// memb(Rs+#s11:0)=Rt
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// memb(Rs+#s11:0)=Rt
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let isPredicable = 1 in
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def STrib : STInst<(outs),
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(ins MEMri:$addr, IntRegs:$src1),
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"memb($addr) = $src1",
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[(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr)]>;
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let AddedComplexity = 10, isPredicable = 1 in
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let AddedComplexity = 10, isPredicable = 1 in
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def STrib_indexed : STInst<(outs),
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def STrib_indexed : STInst<(outs),
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(ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
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(ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
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@ -1773,20 +1809,6 @@ def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
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// Store byte conditionally.
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// Store byte conditionally.
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// if ([!]Pv) memb(Rs+#u6:0)=Rt
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// if ([!]Pv) memb(Rs+#u6:0)=Rt
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// if (Pv) memb(Rs+#u6:0)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STrib_cPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if ($src1) memb($addr) = $src2",
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[]>;
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// if (!Pv) memb(Rs+#u6:0)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STrib_cNotPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if (!$src1) memb($addr) = $src2",
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[]>;
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// if (Pv) memb(Rs+#u6:0)=Rt
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// if (Pv) memb(Rs+#u6:0)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STrib_indexed_cPt : STInst2<(outs),
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def STrib_indexed_cPt : STInst2<(outs),
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@ -1819,13 +1841,6 @@ def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
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// Store halfword.
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// Store halfword.
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// memh(Rs+#s11:1)=Rt
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// memh(Rs+#s11:1)=Rt
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let isPredicable = 1 in
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def STrih : STInst<(outs),
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(ins MEMri:$addr, IntRegs:$src1),
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"memh($addr) = $src1",
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[(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr)]>;
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let AddedComplexity = 10, isPredicable = 1 in
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let AddedComplexity = 10, isPredicable = 1 in
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def STrih_indexed : STInst<(outs),
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def STrih_indexed : STInst<(outs),
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(ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
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(ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
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@ -1860,20 +1875,6 @@ def POST_SThri : STInstPI<(outs IntRegs:$dst),
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// Store halfword conditionally.
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// Store halfword conditionally.
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// if ([!]Pv) memh(Rs+#u6:1)=Rt
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// if ([!]Pv) memh(Rs+#u6:1)=Rt
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// if (Pv) memh(Rs+#u6:1)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STrih_cPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if ($src1) memh($addr) = $src2",
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[]>;
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// if (!Pv) memh(Rs+#u6:1)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STrih_cNotPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if (!$src1) memh($addr) = $src2",
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[]>;
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// if (Pv) memh(Rs+#u6:1)=Rt
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// if (Pv) memh(Rs+#u6:1)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STrih_indexed_cPt : STInst2<(outs),
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def STrih_indexed_cPt : STInst2<(outs),
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@ -1913,12 +1914,6 @@ def STriw_pred : STInst2<(outs),
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[]>;
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[]>;
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// memw(Rs+#s11:2)=Rt
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// memw(Rs+#s11:2)=Rt
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let isPredicable = 1 in
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def STriw : STInst<(outs),
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(ins MEMri:$addr, IntRegs:$src1),
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"memw($addr) = $src1",
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[(store (i32 IntRegs:$src1), ADDRriS11_2:$addr)]>;
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let AddedComplexity = 10, isPredicable = 1 in
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let AddedComplexity = 10, isPredicable = 1 in
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def STriw_indexed : STInst<(outs),
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def STriw_indexed : STInst<(outs),
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(ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
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(ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
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@ -1951,20 +1946,6 @@ def POST_STwri : STInstPI<(outs IntRegs:$dst),
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// Store word conditionally.
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// Store word conditionally.
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// if ([!]Pv) memw(Rs+#u6:2)=Rt
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// if ([!]Pv) memw(Rs+#u6:2)=Rt
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// if (Pv) memw(Rs+#u6:2)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STriw_cPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if ($src1) memw($addr) = $src2",
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[]>;
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// if (!Pv) memw(Rs+#u6:2)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STriw_cNotPt : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if (!$src1) memw($addr) = $src2",
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[]>;
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// if (Pv) memw(Rs+#u6:2)=Rt
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// if (Pv) memw(Rs+#u6:2)=Rt
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let neverHasSideEffects = 1, isPredicated = 1 in
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let neverHasSideEffects = 1, isPredicated = 1 in
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def STriw_indexed_cPt : STInst2<(outs),
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def STriw_indexed_cPt : STInst2<(outs),
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@ -1553,26 +1553,6 @@ def STrid_shl_V4 : STInst<(outs),
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// TODO: needs to be implemented.
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// TODO: needs to be implemented.
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// if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt
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// if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt
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// if (Pv) memd(Rs+#u6:3)=Rtt
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// if (Pv.new) memd(Rs+#u6:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrid_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
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"if ($src1.new) memd($addr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memd(Rs+#u6:3)=Rtt
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// if (!Pv.new) memd(Rs+#u6:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrid_cdnNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
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"if (!$src1.new) memd($addr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) memd(Rs+#u6:3)=Rtt
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// if (Pv) memd(Rs+#u6:3)=Rtt
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// if (Pv.new) memd(Rs+#u6:3)=Rtt
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// if (Pv.new) memd(Rs+#u6:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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let AddedComplexity = 10, neverHasSideEffects = 1,
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@ -1738,26 +1718,6 @@ def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
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Requires<[HasV4T]>;
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Requires<[HasV4T]>;
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// if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt
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// if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt
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// if (Pv) memb(Rs+#u6:0)=Rt
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// if (Pv.new) memb(Rs+#u6:0)=Rt
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if ($src1.new) memb($addr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memb(Rs+#u6:0)=Rt
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// if (!Pv.new) memb(Rs+#u6:0)=Rt
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_cdnNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if (!$src1.new) memb($addr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) memb(Rs+#u6:0)=Rt
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// if (Pv) memb(Rs+#u6:0)=Rt
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// if (!Pv) memb(Rs+#u6:0)=Rt
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// if (!Pv) memb(Rs+#u6:0)=Rt
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// if (Pv.new) memb(Rs+#u6:0)=Rt
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// if (Pv.new) memb(Rs+#u6:0)=Rt
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@ -1932,26 +1892,6 @@ def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
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// TODO: needs to be implemented.
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// TODO: needs to be implemented.
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// if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt
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// if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt
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// if (Pv) memh(Rs+#u6:1)=Rt
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// if (Pv.new) memh(Rs+#u6:1)=Rt
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
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"if ($src1.new) memh($addr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memh(Rs+#u6:1)=Rt
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// if (!Pv.new) memh(Rs+#u6:1)=Rt
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let neverHasSideEffects = 1,
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isPredicated = 1 in
|
|
||||||
def STrih_cdnNotPt_V4 : STInst2<(outs),
|
|
||||||
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
|
|
||||||
"if (!$src1.new) memh($addr) = $src2",
|
|
||||||
[]>,
|
|
||||||
Requires<[HasV4T]>;
|
|
||||||
|
|
||||||
// if (Pv.new) memh(Rs+#u6:1)=Rt
|
// if (Pv.new) memh(Rs+#u6:1)=Rt
|
||||||
let neverHasSideEffects = 1,
|
let neverHasSideEffects = 1,
|
||||||
isPredicated = 1 in
|
isPredicated = 1 in
|
||||||
@ -2127,26 +2067,6 @@ def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
|
|||||||
Requires<[HasV4T]>;
|
Requires<[HasV4T]>;
|
||||||
|
|
||||||
// if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt
|
// if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt
|
||||||
// if (Pv) memw(Rs+#u6:2)=Rt
|
|
||||||
// if (Pv.new) memw(Rs+#u6:2)=Rt
|
|
||||||
let neverHasSideEffects = 1,
|
|
||||||
isPredicated = 1 in
|
|
||||||
def STriw_cdnPt_V4 : STInst2<(outs),
|
|
||||||
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
|
|
||||||
"if ($src1.new) memw($addr) = $src2",
|
|
||||||
[]>,
|
|
||||||
Requires<[HasV4T]>;
|
|
||||||
|
|
||||||
// if (!Pv) memw(Rs+#u6:2)=Rt
|
|
||||||
// if (!Pv.new) memw(Rs+#u6:2)=Rt
|
|
||||||
let neverHasSideEffects = 1,
|
|
||||||
isPredicated = 1 in
|
|
||||||
def STriw_cdnNotPt_V4 : STInst2<(outs),
|
|
||||||
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
|
|
||||||
"if (!$src1.new) memw($addr) = $src2",
|
|
||||||
[]>,
|
|
||||||
Requires<[HasV4T]>;
|
|
||||||
|
|
||||||
// if (Pv) memw(Rs+#u6:2)=Rt
|
// if (Pv) memw(Rs+#u6:2)=Rt
|
||||||
// if (!Pv) memw(Rs+#u6:2)=Rt
|
// if (!Pv) memw(Rs+#u6:2)=Rt
|
||||||
// if (Pv.new) memw(Rs+#u6:2)=Rt
|
// if (Pv.new) memw(Rs+#u6:2)=Rt
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user