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Patch by Gordon Keiser!

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If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.

This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joe Abbey 2013-03-26 13:58:53 +00:00
parent ca825ea24d
commit b78821d380
2 changed files with 3 additions and 1 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -3278,7 +3278,7 @@ static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
}
if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (load) {

2
test/MC/Disassembler/ARM/thumb2.txt
View File

@ -554,6 +554,7 @@
# CHECK: ldr.w r8, [r8, r2, lsl #2]
# CHECK: ldr.w r7, [sp, r2, lsl #1]
# CHECK: ldr.w r7, [sp, r2]
# CHECK: ldr pc, [sp], #12
# CHECK: ldr r2, [r4, #255]!
# CHECK: ldr r8, [sp, #4]!
# CHECK: ldr lr, [sp, #-4]!
@ -567,6 +568,7 @@
0x58 0xf8 0x22 0x80
0x5d 0xf8 0x12 0x70
0x5d 0xf8 0x02 0x70
0x5d 0xf8 0x0c 0xfb
0x54 0xf8 0xff 0x2f
0x5d 0xf8 0x04 0x8f
0x5d 0xf8 0x04 0xed