6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-30 02:32:08 +00:00
Code Issues Projects Releases Wiki Activity

Fix comment.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100259 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-04-03 01:17:30 +00:00
parent b35ae7f7d6
commit b7aaed83e2
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -478,7 +478,7 @@ static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
/// followed by possible src(s).
///
/// The processing of the predicate, and the 'S' modifier bit, if MI modifies
/// the CPSR, is factored into ARMBasicMCBuilder's class method named
/// the CPSR, is factored into ARMBasicMCBuilder's method named
/// TryPredicateAndSBitModifier.
static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
@ -3159,7 +3159,7 @@ ARMAlgorithm *ARMAlgorithm::GetInstance(ARMFormat Format) {
/// The general idea is to set the Opcode for the MCInst, followed by adding
/// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
/// to the Algo (ARM Disassemble Algorithm) object to perform Format-specific
/// disassembly, followed by class method TryPredicateAndSBitModifier() to do
/// disassembly, followed by TryPredicateAndSBitModifier() to do
/// PredicateOperand and OptionalDefOperand which follow the Dst/Src Operands.
bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
// Stage 1 sets the Opcode.