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Revert 233694. Weak SVN-fu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233695 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -15,7 +15,6 @@ add_llvm_target(HexagonCodeGen
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HexagonAsmPrinter.cpp
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HexagonAsmPrinter.cpp
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HexagonCFGOptimizer.cpp
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HexagonCFGOptimizer.cpp
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HexagonCopyToCombine.cpp
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HexagonCopyToCombine.cpp
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HexagonExpandCondsets.cpp
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HexagonExpandPredSpillCode.cpp
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HexagonExpandPredSpillCode.cpp
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HexagonFixupHwLoops.cpp
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HexagonFixupHwLoops.cpp
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HexagonFrameLowering.cpp
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HexagonFrameLowering.cpp
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@ -845,7 +845,8 @@ bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
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return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
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return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
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}
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}
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int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
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int HexagonInstrInfo::
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getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
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enum Hexagon::PredSense inPredSense;
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enum Hexagon::PredSense inPredSense;
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inPredSense = invertPredicate ? Hexagon::PredSense_false :
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inPredSense = invertPredicate ? Hexagon::PredSense_false :
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Hexagon::PredSense_true;
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Hexagon::PredSense_true;
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@ -883,7 +884,7 @@ PredicateInstruction(MachineInstr *MI,
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// This will change MI's opcode to its predicate version.
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// This will change MI's opcode to its predicate version.
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// However, its operand list is still the old one, i.e. the
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// However, its operand list is still the old one, i.e. the
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// non-predicate one.
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// non-predicate one.
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MI->setDesc(get(getCondOpcode(Opc, invertJump)));
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MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
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int oper = -1;
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int oper = -1;
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unsigned int GAIdx = 0;
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unsigned int GAIdx = 0;
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@ -216,7 +216,9 @@ public:
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short getNonExtOpcode(const MachineInstr *MI) const;
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short getNonExtOpcode(const MachineInstr *MI) const;
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bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
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bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
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bool PredOpcodeHasNot(Opcode_t Opcode) const;
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bool PredOpcodeHasNot(Opcode_t Opcode) const;
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int getCondOpcode(int Opc, bool sense) const;
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private:
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int getMatchingCondBranchOpcode(int Opc, bool sense) const;
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};
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};
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@ -27,15 +27,11 @@
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using namespace llvm;
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using namespace llvm;
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static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon CFG Optimization"));
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cl::desc("Disable Hexagon CFG Optimization"));
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static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
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cl::init(true), cl::Hidden, cl::ZeroOrMore,
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cl::desc("Early expansion of MUX"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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@ -59,10 +55,6 @@ static MachineSchedRegistry
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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createVLIWMachineSched);
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namespace llvm {
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FunctionPass *createHexagonExpandCondsets();
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}
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/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
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/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
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///
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///
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@ -87,15 +79,7 @@ namespace {
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class HexagonPassConfig : public TargetPassConfig {
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class HexagonPassConfig : public TargetPassConfig {
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public:
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public:
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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: TargetPassConfig(TM, PM) {}
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bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
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if (!NoOpt) {
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if (EnableExpandCondsets) {
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Pass *Exp = createHexagonExpandCondsets();
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insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
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}
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}
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}
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HexagonTargetMachine &getHexagonTargetMachine() const {
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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return getTM<HexagonTargetMachine>();
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: r{{[0-9]+:[0-9]+}} = #0
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; CHECK: r{{[0-9]+:[0-9]+}} = #0
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; CHECK: r{{[0-9]+:[0-9]+}} = #1
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; CHECK: r{{[0-9]+:[0-9]+}} = #1
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: r{{[0-9]+:[0-9]+}} = #0
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; CHECK: r{{[0-9]+:[0-9]+}} = #0
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; CHECK: r{{[0-9]+:[0-9]+}} = #1
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; CHECK: r{{[0-9]+:[0-9]+}} = #1
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@ -7,4 +7,4 @@ define i32 @foo (i1 %a, i32 %b, i32 %c)
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ret i32 %1
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ret i32 %1
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}
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}
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; CHECK: 0000 00400085 00600174 00608274 00c09f52
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; CHECK: 0000 00400085 004201f4 00c09f52
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