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misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -272,6 +272,9 @@ namespace llvm {
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unsigned Depth; // Node depth.
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unsigned Height; // Node height.
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public:
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unsigned TopReadyCycle; // Cycle relative to start when node is ready.
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unsigned BotReadyCycle; // Cycle relative to end when node is ready.
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const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
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const TargetRegisterClass *CopySrcRC;
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@ -287,7 +290,7 @@ namespace llvm {
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isScheduleHigh(false), isScheduleLow(false), isCloned(false),
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SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
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/// a MachineInstr.
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@ -301,7 +304,7 @@ namespace llvm {
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isScheduleHigh(false), isScheduleLow(false), isCloned(false),
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SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// SUnit - Construct a placeholder SUnit.
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SUnit()
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@ -314,7 +317,7 @@ namespace llvm {
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isScheduleHigh(false), isScheduleLow(false), isCloned(false),
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SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// setNode - Assign the representative SDNode for this SUnit.
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/// This may be used during pre-regalloc scheduling.
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@ -552,12 +555,6 @@ namespace llvm {
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///
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virtual void computeLatency(SUnit *SU) = 0;
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/// ComputeOperandLatency - Override dependence edge latency using
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/// operand use/def information
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///
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virtual void computeOperandLatency(SUnit *, SUnit *,
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SDep&) const { }
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/// ForceUnitLatencies - Return true if all scheduling edges should be given
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/// a latency value of one. The default is to return false; schedulers may
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/// override this as needed.
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@ -291,11 +291,15 @@ namespace llvm {
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///
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virtual void computeLatency(SUnit *SU);
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/// computeOperandLatency - Override dependence edge latency using
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/// computeOperandLatency - Return dependence edge latency using
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/// operand use/def information
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///
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virtual void computeOperandLatency(SUnit *Def, SUnit *Use,
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SDep& dep) const;
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/// FindMin may be set to get the minimum vs. expected latency. Minimum
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/// latency is used for scheduling groups, while expected latency is for
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/// instruction cost and critical path.
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virtual unsigned computeOperandLatency(SUnit *Def, SUnit *Use,
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const SDep& dep,
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bool FindMin = false) const;
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/// schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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@ -214,6 +214,12 @@ public:
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/// class. The latency is the maximum completion time for any stage
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/// in the itinerary.
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///
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/// InstrStages override the itinerary's MinLatency property. In fact, if the
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/// stage latencies, which may be zero, are less than MinLatency,
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/// getStageLatency returns a value less than MinLatency.
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///
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/// If no stages exist, MinLatency is used. If MinLatency is invalid (<0),
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/// then it defaults to one cycle.
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unsigned getStageLatency(unsigned ItinClassIndx) const {
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// If the target doesn't provide itinerary information, use a simple
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// non-zero default value for all instructions. Some target's provide a
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@ -222,7 +228,7 @@ public:
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// stage). This is different from beginStage == endStage != 0, which could
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// be used for zero-latency pseudo ops.
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if (isEmpty() || Itineraries[ItinClassIndx].FirstStage == 0)
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return 1;
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return (Props.MinLatency < 0) ? 1 : Props.MinLatency;
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// Calculate the maximum completion time for any stage.
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unsigned Latency = 0, StartCycle = 0;
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@ -668,18 +668,36 @@ public:
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return Opcode <= TargetOpcode::COPY;
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}
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virtual int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const = 0;
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/// getOperandLatency - Compute and return the use operand latency of a given
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/// pair of def and use.
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/// In most cases, the static scheduling itinerary was enough to determine the
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/// operand latency. But it may not be possible for instructions with variable
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/// number of defs / uses.
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///
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/// This is a raw interface to the itinerary that may be directly overriden by
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/// a target. Use computeOperandLatency to get the best estimate of latency.
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virtual int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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const MachineInstr *UseMI,
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unsigned UseIdx) const;
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virtual int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const = 0;
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/// computeOperandLatency - Compute and return the latency of the given data
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/// dependent def and use. DefMI must be a valid def. UseMI may be NULL for
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/// an unknown use. If the subtarget allows, this may or may not need to call
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/// getOperandLatency().
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///
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/// FindMin may be set to get the minimum vs. expected latency. Minimum
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/// latency is used for scheduling groups, while expected latency is for
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/// instruction cost and critical path.
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unsigned computeOperandLatency(const InstrItineraryData *ItinData,
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const TargetRegisterInfo *TRI,
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const MachineInstr *DefMI,
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const MachineInstr *UseMI,
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unsigned Reg, bool FindMin) const;
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/// getOutputLatency - Compute and return the output dependency latency of a
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/// a given pair of defs which both target the same register. This is usually
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@ -693,13 +711,17 @@ public:
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/// getInstrLatency - Compute the instruction latency of a given instruction.
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/// If the instruction has higher cost when predicated, it's returned via
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/// PredCost.
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virtual int getInstrLatency(const InstrItineraryData *ItinData,
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virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost = 0) const;
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virtual int getInstrLatency(const InstrItineraryData *ItinData,
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SDNode *Node) const = 0;
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/// Return the default expected latency for a def based on it's opcode.
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unsigned defaultDefLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI) const;
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/// isHighLatencyDef - Return true if this opcode has high latency to its
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/// result.
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virtual bool isHighLatencyDef(int opc) const { return false; }
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@ -21,8 +21,9 @@
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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@ -394,6 +395,12 @@ public:
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return RegionCriticalPSets;
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}
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/// getIssueWidth - Return the max instructions per scheduling group.
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///
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unsigned getIssueWidth() const {
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return InstrItins ? InstrItins->Props.IssueWidth : 1;
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}
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protected:
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void initRegPressure();
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void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
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@ -787,13 +794,16 @@ class ConvergingScheduler : public MachineSchedStrategy {
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/// MinReadyCycle - Cycle of the soonest available instruction.
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unsigned MinReadyCycle;
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// Remember the greatest min operand latency.
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unsigned MaxMinLatency;
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/// Pending queues extend the ready queues with the same ID and the
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/// PendingFlag set.
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SchedBoundary(unsigned ID, const Twine &Name):
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Available(ID, Name+".A"),
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Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
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CheckPending(false), HazardRec(0), CurrCycle(0), IssueCount(0),
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MinReadyCycle(UINT_MAX) {}
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MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
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~SchedBoundary() { delete HazardRec; }
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@ -805,6 +815,8 @@ class ConvergingScheduler : public MachineSchedStrategy {
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void bumpCycle();
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void bumpNode(SUnit *SU, unsigned IssueWidth);
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void releasePending();
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void removeReady(SUnit *SU);
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@ -868,25 +880,53 @@ void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
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}
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void ConvergingScheduler::releaseTopNode(SUnit *SU) {
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Top.releaseNode(SU, SU->getDepth());
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if (SU->isScheduled)
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return;
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for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
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unsigned Latency =
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DAG->computeOperandLatency(I->getSUnit(), SU, *I, /*FindMin=*/true);
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#ifndef NDEBUG
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Top.MaxMinLatency = std::max(Latency, Top.MaxMinLatency);
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#endif
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if (SU->TopReadyCycle < PredReadyCycle + Latency)
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SU->TopReadyCycle = PredReadyCycle + Latency;
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}
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Top.releaseNode(SU, SU->TopReadyCycle);
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}
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void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
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Bot.releaseNode(SU, SU->getHeight());
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if (SU->isScheduled)
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return;
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assert(SU->getInstr() && "Scheduled SUnit must have instr");
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
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unsigned Latency =
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DAG->computeOperandLatency(SU, I->getSUnit(), *I, /*FindMin=*/true);
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#ifndef NDEBUG
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Bot.MaxMinLatency = std::max(Latency, Bot.MaxMinLatency);
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#endif
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if (SU->BotReadyCycle < SuccReadyCycle + Latency)
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SU->BotReadyCycle = SuccReadyCycle + Latency;
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}
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Bot.releaseNode(SU, SU->BotReadyCycle);
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}
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void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
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unsigned ReadyCycle) {
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if (SU->isScheduled)
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return;
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if (ReadyCycle < MinReadyCycle)
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MinReadyCycle = ReadyCycle;
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// Check for interlocks first. For the purpose of other heuristics, an
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// instruction that cannot issue appears as if it's not in the ReadyQueue.
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if (HazardRec->isEnabled()
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&& HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard)
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if (ReadyCycle > CurrCycle
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|| (HazardRec->isEnabled() && (HazardRec->getHazardType(SU)
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!= ScheduleHazardRecognizer::NoHazard)))
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Pending.push(SU);
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else
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Available.push(SU);
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@ -900,10 +940,11 @@ void ConvergingScheduler::SchedBoundary::bumpCycle() {
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unsigned NextCycle = std::max(CurrCycle + 1, MinReadyCycle);
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if (!HazardRec->isEnabled()) {
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// Bypass lots of virtual calls in case of long latency.
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// Bypass HazardRec virtual calls.
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CurrCycle = NextCycle;
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}
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else {
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// Bypass getHazardType calls in case of long latency.
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for (; CurrCycle != NextCycle; ++CurrCycle) {
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if (isTop())
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HazardRec->AdvanceCycle();
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@ -917,6 +958,26 @@ void ConvergingScheduler::SchedBoundary::bumpCycle() {
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<< CurrCycle << '\n');
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}
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/// Move the boundary of scheduled code by one SUnit.
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void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU,
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unsigned IssueWidth) {
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// Update the reservation table.
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if (HazardRec->isEnabled()) {
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if (!isTop() && SU->isCall) {
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// Calls are scheduled with their preceding instructions. For bottom-up
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// scheduling, clear the pipeline state before emitting.
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HazardRec->Reset();
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}
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HazardRec->EmitInstruction(SU);
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}
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// Check the instruction group size limit.
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++IssueCount;
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if (IssueCount == IssueWidth) {
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DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n');
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bumpCycle();
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}
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}
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/// Release pending ready nodes in to the available queue. This makes them
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/// visible to heuristics.
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void ConvergingScheduler::SchedBoundary::releasePending() {
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@ -928,7 +989,7 @@ void ConvergingScheduler::SchedBoundary::releasePending() {
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// so, add them to the available queue.
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for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
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SUnit *SU = *(Pending.begin()+i);
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unsigned ReadyCycle = isTop() ? SU->getHeight() : SU->getDepth();
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unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
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if (ReadyCycle < MinReadyCycle)
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MinReadyCycle = ReadyCycle;
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@ -965,7 +1026,8 @@ SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
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releasePending();
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for (unsigned i = 0; Available.empty(); ++i) {
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assert(i <= HazardRec->getMaxLookAhead() && "permanent hazard"); (void)i;
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assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
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"permanent hazard"); (void)i;
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bumpCycle();
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releasePending();
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}
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@ -1205,27 +1267,15 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
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/// Update the scheduler's state after scheduling a node. This is the same node
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/// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
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/// it's state based on the current cycle before MachineSchedStrategy.
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/// it's state based on the current cycle before MachineSchedStrategy does.
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void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
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// Update the reservation table.
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if (IsTopNode && Top.HazardRec->isEnabled()) {
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Top.HazardRec->EmitInstruction(SU);
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if (Top.HazardRec->atIssueLimit()) {
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DEBUG(dbgs() << "*** Max instrs at cycle " << Top.CurrCycle << '\n');
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Top.bumpCycle();
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}
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}
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else if (Bot.HazardRec->isEnabled()) {
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if (SU->isCall) {
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// Calls are scheduled with their preceding instructions. For bottom-up
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// scheduling, clear the pipeline state before emitting.
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Bot.HazardRec->Reset();
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}
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Bot.HazardRec->EmitInstruction(SU);
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if (Bot.HazardRec->atIssueLimit()) {
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DEBUG(dbgs() << "*** Max instrs at cycle " << Bot.CurrCycle << '\n');
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Bot.bumpCycle();
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if (IsTopNode) {
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SU->TopReadyCycle = Top.CurrCycle;
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Top.bumpNode(SU, DAG->getIssueWidth());
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}
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else {
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SU->BotReadyCycle = Bot.CurrCycle;
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Bot.bumpNode(SU, DAG->getIssueWidth());
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}
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}
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@ -271,10 +271,12 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU,
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// Adjust the dependence latency using operand def/use
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// information (if any), and then allow the target to
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// perform its own adjustments.
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const SDep& dep = SDep(SU, SDep::Data, LDataLatency, *Alias);
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SDep dep(SU, SDep::Data, LDataLatency, *Alias);
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if (!UnitLatencies) {
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computeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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unsigned Latency = computeOperandLatency(SU, UseSU, dep);
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dep.setLatency(Latency);
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ST.adjustSchedDependency(SU, UseSU, dep);
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}
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UseSU->addPred(dep);
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}
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@ -461,11 +463,13 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
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// Create a data dependence.
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//
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// TODO: Handle "special" address latencies cleanly.
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const SDep &dep = SDep(DefSU, SDep::Data, DefSU->Latency, Reg);
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SDep dep(DefSU, SDep::Data, DefSU->Latency, Reg);
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if (!UnitLatencies) {
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// Adjust the dependence latency using operand def/use information, then
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// allow the target to perform its own adjustments.
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computeOperandLatency(DefSU, SU, const_cast<SDep &>(dep));
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unsigned Latency = computeOperandLatency(DefSU, SU, const_cast<SDep &>(dep));
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dep.setLatency(Latency);
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
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}
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@ -970,8 +974,9 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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}
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void ScheduleDAGInstrs::computeLatency(SUnit *SU) {
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// Compute the latency for the node.
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if (!InstrItins || InstrItins->isEmpty()) {
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// Compute the latency for the node. We only provide a default for missing
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// itineraries. Empty itineraries still have latency properties.
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if (!InstrItins) {
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SU->Latency = 1;
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// Simplistic target-independent heuristic: assume that loads take
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@ -983,63 +988,15 @@ void ScheduleDAGInstrs::computeLatency(SUnit *SU) {
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}
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}
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void ScheduleDAGInstrs::computeOperandLatency(SUnit *Def, SUnit *Use,
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SDep& dep) const {
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if (!InstrItins || InstrItins->isEmpty())
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return;
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unsigned ScheduleDAGInstrs::computeOperandLatency(SUnit *Def, SUnit *Use,
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const SDep& dep,
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bool FindMin) const {
|
||||
// For a data dependency with a known register...
|
||||
if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
|
||||
return;
|
||||
return 1;
|
||||
|
||||
const unsigned Reg = dep.getReg();
|
||||
|
||||
// ... find the definition of the register in the defining
|
||||
// instruction
|
||||
MachineInstr *DefMI = Def->getInstr();
|
||||
int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
|
||||
if (DefIdx != -1) {
|
||||
const MachineOperand &MO = DefMI->getOperand(DefIdx);
|
||||
if (MO.isReg() && MO.isImplicit() &&
|
||||
DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
|
||||
// This is an implicit def, getOperandLatency() won't return the correct
|
||||
// latency. e.g.
|
||||
// %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
|
||||
// %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
|
||||
// What we want is to compute latency between def of %D6/%D7 and use of
|
||||
// %Q3 instead.
|
||||
unsigned Op2 = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
|
||||
if (DefMI->getOperand(Op2).isReg())
|
||||
DefIdx = Op2;
|
||||
}
|
||||
MachineInstr *UseMI = Use->getInstr();
|
||||
// For all uses of the register, calculate the maxmimum latency
|
||||
int Latency = -1;
|
||||
if (UseMI) {
|
||||
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO = UseMI->getOperand(i);
|
||||
if (!MO.isReg() || !MO.isUse())
|
||||
continue;
|
||||
unsigned MOReg = MO.getReg();
|
||||
if (MOReg != Reg)
|
||||
continue;
|
||||
|
||||
int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
|
||||
UseMI, i);
|
||||
Latency = std::max(Latency, UseCycle);
|
||||
}
|
||||
} else {
|
||||
// UseMI is null, then it must be a scheduling barrier.
|
||||
if (!InstrItins || InstrItins->isEmpty())
|
||||
return;
|
||||
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
||||
Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
|
||||
}
|
||||
|
||||
// If we found a latency, then replace the existing dependence latency.
|
||||
if (Latency >= 0)
|
||||
dep.setLatency(Latency);
|
||||
}
|
||||
return TII->computeOperandLatency(InstrItins, TRI, Def->getInstr(),
|
||||
Use->getInstr(), dep.getReg(), FindMin);
|
||||
}
|
||||
|
||||
void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
|
||||
|
@ -98,12 +98,6 @@ namespace llvm {
|
||||
///
|
||||
virtual void computeLatency(SUnit *SU);
|
||||
|
||||
/// computeOperandLatency - Override dependence edge latency using
|
||||
/// operand use/def information
|
||||
///
|
||||
virtual void computeOperandLatency(SUnit *Def, SUnit *Use,
|
||||
SDep& dep) const { }
|
||||
|
||||
virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
|
||||
unsigned OpIdx, SDep& dep) const;
|
||||
|
||||
|
@ -1046,7 +1046,7 @@ bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
|
||||
return true; // Below MI
|
||||
unsigned DefDist = DDI->second;
|
||||
assert(Dist > DefDist && "Visited def already?");
|
||||
if (TII->getInstrLatency(InstrItins, DefMI) > (int)(Dist - DefDist))
|
||||
if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
|
@ -2568,11 +2568,12 @@ static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
|
||||
int
|
||||
ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *DefMI, unsigned DefIdx,
|
||||
const MachineInstr *UseMI, unsigned UseIdx) const {
|
||||
const MachineInstr *UseMI,
|
||||
unsigned UseIdx) const {
|
||||
if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
|
||||
DefMI->isRegSequence() || DefMI->isImplicitDef())
|
||||
DefMI->isRegSequence() || DefMI->isImplicitDef()) {
|
||||
return 1;
|
||||
|
||||
}
|
||||
if (!ItinData || ItinData->isEmpty())
|
||||
return DefMI->mayLoad() ? 3 : 1;
|
||||
|
||||
@ -2983,14 +2984,16 @@ ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
|
||||
DepMI->getNumOperands());
|
||||
}
|
||||
|
||||
int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
||||
unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *MI,
|
||||
unsigned *PredCost) const {
|
||||
if (MI->isCopyLike() || MI->isInsertSubreg() ||
|
||||
MI->isRegSequence() || MI->isImplicitDef())
|
||||
return 1;
|
||||
|
||||
if (!ItinData || ItinData->isEmpty())
|
||||
// Be sure to call getStageLatency for an empty itinerary in case it has a
|
||||
// valid MinLatency property.
|
||||
if (!ItinData)
|
||||
return 1;
|
||||
|
||||
if (MI->isBundle()) {
|
||||
|
@ -249,8 +249,9 @@ private:
|
||||
const MCInstrDesc &UseMCID,
|
||||
unsigned UseIdx, unsigned UseAlign) const;
|
||||
|
||||
int getInstrLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *MI, unsigned *PredCost = 0) const;
|
||||
unsigned getInstrLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *MI,
|
||||
unsigned *PredCost = 0) const;
|
||||
|
||||
int getInstrLatency(const InstrItineraryData *ItinData,
|
||||
SDNode *Node) const;
|
||||
|
@ -61,22 +61,125 @@ TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
|
||||
return 1;
|
||||
}
|
||||
|
||||
/// Return the default expected latency for a def based on it's opcode.
|
||||
unsigned TargetInstrInfo::defaultDefLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *DefMI) const {
|
||||
if (DefMI->mayLoad())
|
||||
return ItinData->Props.LoadLatency;
|
||||
if (isHighLatencyDef(DefMI->getOpcode()))
|
||||
return ItinData->Props.HighLatency;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/// Both DefMI and UseMI must be valid. By default, call directly to the
|
||||
/// itinerary. This may be overriden by the target.
|
||||
int
|
||||
TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *DefMI, unsigned DefIdx,
|
||||
const MachineInstr *UseMI, unsigned UseIdx) const {
|
||||
if (!ItinData || ItinData->isEmpty())
|
||||
return -1;
|
||||
|
||||
const MachineInstr *UseMI,
|
||||
unsigned UseIdx) const {
|
||||
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
||||
unsigned UseClass = UseMI->getDesc().getSchedClass();
|
||||
return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
||||
}
|
||||
|
||||
int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
||||
/// computeOperandLatency - Compute and return the latency of the given data
|
||||
/// dependent def and use. DefMI must be a valid def. UseMI may be NULL for an
|
||||
/// unknown use. Depending on the subtarget's itinerary properties, this may or
|
||||
/// may not need to call getOperandLatency().
|
||||
///
|
||||
/// FindMin may be set to get the minimum vs. expected latency. Minimum
|
||||
/// latency is used for scheduling groups, while expected latency is for
|
||||
/// instruction cost and critical path.
|
||||
///
|
||||
/// For most subtargets, we don't need DefIdx or UseIdx to compute min latency.
|
||||
/// DefMI must be a valid definition, but UseMI may be NULL for an unknown use.
|
||||
unsigned TargetInstrInfo::
|
||||
computeOperandLatency(const InstrItineraryData *ItinData,
|
||||
const TargetRegisterInfo *TRI,
|
||||
const MachineInstr *DefMI, const MachineInstr *UseMI,
|
||||
unsigned Reg, bool FindMin) const {
|
||||
|
||||
// Default to one cycle for missing itinerary. Empty itineraries still have
|
||||
// a properties. We have one hard-coded exception for loads, to preserve
|
||||
// existing behavior.
|
||||
if (!ItinData)
|
||||
return DefMI->mayLoad() ? 2 : 1;
|
||||
|
||||
// Return a latency based on the itinerary properties and defining instruction
|
||||
// if possible. Some common subtargets don't require per-operand latency,
|
||||
// especially for minimum latencies.
|
||||
if (FindMin) {
|
||||
// If MinLatency is valid, call getInstrLatency. This uses Stage latency if
|
||||
// it exists before defaulting to MinLatency.
|
||||
if (ItinData->Props.MinLatency >= 0)
|
||||
return getInstrLatency(ItinData, DefMI);
|
||||
|
||||
// If MinLatency is invalid, OperandLatency is interpreted as MinLatency.
|
||||
// For empty itineraries, short-cirtuit the check and default to one cycle.
|
||||
if (ItinData->isEmpty())
|
||||
return 1;
|
||||
}
|
||||
else if(ItinData->isEmpty())
|
||||
return defaultDefLatency(ItinData, DefMI);
|
||||
|
||||
// ...operand lookup required
|
||||
|
||||
// Find the definition of the register in the defining instruction.
|
||||
int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
|
||||
if (DefIdx != -1) {
|
||||
const MachineOperand &MO = DefMI->getOperand(DefIdx);
|
||||
if (MO.isReg() && MO.isImplicit() &&
|
||||
DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
|
||||
// This is an implicit def, getOperandLatency() won't return the correct
|
||||
// latency. e.g.
|
||||
// %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
|
||||
// %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
|
||||
// What we want is to compute latency between def of %D6/%D7 and use of
|
||||
// %Q3 instead.
|
||||
unsigned Op2 = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
|
||||
if (DefMI->getOperand(Op2).isReg())
|
||||
DefIdx = Op2;
|
||||
}
|
||||
// For all uses of the register, calculate the maxmimum latency
|
||||
int OperLatency = -1;
|
||||
|
||||
// UseMI is null, then it must be a scheduling barrier.
|
||||
if (!UseMI) {
|
||||
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
||||
OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
|
||||
}
|
||||
else {
|
||||
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO = UseMI->getOperand(i);
|
||||
if (!MO.isReg() || !MO.isUse())
|
||||
continue;
|
||||
unsigned MOReg = MO.getReg();
|
||||
if (MOReg != Reg)
|
||||
continue;
|
||||
|
||||
int UseCycle = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, i);
|
||||
OperLatency = std::max(OperLatency, UseCycle);
|
||||
}
|
||||
}
|
||||
// If we found an operand latency, we're done.
|
||||
if (OperLatency >= 0)
|
||||
return OperLatency;
|
||||
}
|
||||
// No operand latency was found.
|
||||
unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
|
||||
// Expected latency is the max of the stage latency and itinerary props.
|
||||
if (!FindMin)
|
||||
InstrLatency = std::max(InstrLatency, defaultDefLatency(ItinData, DefMI));
|
||||
return InstrLatency;
|
||||
}
|
||||
|
||||
unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *MI,
|
||||
unsigned *PredCost) const {
|
||||
if (!ItinData || ItinData->isEmpty())
|
||||
// Default to one cycle for no itinerary. However, an "empty" itinerary may
|
||||
// still have a MinLatency property, which getStageLatency checks.
|
||||
if (!ItinData)
|
||||
return 1;
|
||||
|
||||
return ItinData->getStageLatency(MI->getDesc().getSchedClass());
|
||||
|
Loading…
Reference in New Issue
Block a user