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Don't spill PPC VRSAVE on non-Darwin (even in SjLj)

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As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore
VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've
added some asserts to make sure that we're not).

As it turns out, we're not currently handling the Darwin case correctly (I've
added a FIXME in the test case). I've tried adding various implied register
definitions/uses to force the spill without success, so I'll need to address
this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178096 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-27 00:02:20 +00:00
parent ca442a4a1a
commit b7e11e400d
5 changed files with 18 additions and 6 deletions
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3
lib/Target/PowerPC/PPCCallingConv.td
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@ -137,7 +137,8 @@ def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAV
V20, V21, V22, V23, V24, V25, V26, V27, V20, V21, V22, V23, V24, V25, V26, V27,
V28, V29, V30, V31)>; V28, V29, V30, V31)>;
def CSR_NoRegs : CalleeSavedRegs<(add)>; def CSR_NoRegs : CalleeSavedRegs<(add VRSAVE)>;
def CSR_NoRegs_Darwin : CalleeSavedRegs<(add)>;
def CSR_NoRegs_Altivec : CalleeSavedRegs<(add (sequence "V%u", 0, 31), VRSAVE)>; def CSR_NoRegs_Altivec : CalleeSavedRegs<(add (sequence "V%u", 0, 31), VRSAVE)>;

4
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -509,6 +509,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
FrameIdx)); FrameIdx));
NonRI = true; NonRI = true;
} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
assert(TM.getSubtargetImpl()->isDarwin() &&
"VRSAVE only needs spill/restore on Darwin");
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
.addReg(SrcReg, .addReg(SrcReg,
getKillRegState(isKill)), getKillRegState(isKill)),
@ -627,6 +629,8 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
FrameIdx)); FrameIdx));
NonRI = true; NonRI = true;
} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
assert(TM.getSubtargetImpl()->isDarwin() &&
"VRSAVE only needs spill/restore on Darwin");
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
get(PPC::RESTORE_VRSAVE), get(PPC::RESTORE_VRSAVE),
DestReg), DestReg),

2
lib/Target/PowerPC/PPCRegisterInfo.cpp
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@ -114,6 +114,8 @@ PPCRegisterInfo::getNoPreservedMask() const {
if (!Subtarget.hasAltivec()) if (!Subtarget.hasAltivec())
return CSR_NoRegs_Altivec_RegMask; return CSR_NoRegs_Altivec_RegMask;
if (Subtarget.isDarwin())
return CSR_NoRegs_Darwin_RegMask;
return CSR_NoRegs_RegMask; return CSR_NoRegs_RegMask;
} }

4
test/CodeGen/PowerPC/sjlj.ll
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@ -57,8 +57,12 @@ return: ; preds = %if.end, %if.then
%3 = load i32* %retval %3 = load i32* %retval
ret i32 %3 ret i32 %3
; FIXME: We should be saving VRSAVE on Darwin, but we're not!
; CHECK: @main ; CHECK: @main
; CHECK: std ; CHECK: std
; Make sure that we're not saving VRSAVE on non-Darwin:
; CHECK-NOT: mfspr
; CHECK: stfd ; CHECK: stfd
; CHECK: stvx ; CHECK: stvx

11
test/CodeGen/PowerPC/vrsave-spill.ll
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@ -1,18 +1,19 @@
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64-apple-darwin -mcpu=g5 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-apple-darwin"
define <4 x float> @foo(<4 x float> %a, <4 x float> %b) nounwind { define <4 x float> @foo(<4 x float> %a, <4 x float> %b) nounwind {
entry: entry:
%c = fadd <4 x float> %a, %b %c = fadd <4 x float> %a, %b
%d = fmul <4 x float> %c, %a
call void asm sideeffect "", "~{VRsave}"() nounwind call void asm sideeffect "", "~{VRsave}"() nounwind
br label %return br label %return
; CHECK: @foo ; CHECK: @foo
; CHECK: mfspr {{[0-9]+}}, 256 ; CHECK: mfspr r{{[0-9]+}}, 256
; CHECK: mtspr 256, {{[0-9]+}} ; CHECK: mtspr 256, r{{[0-9]+}}
return: ; preds = %entry return: ; preds = %entry
ret <4 x float> %c ret <4 x float> %d
} }