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scheduler update
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115515 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -734,12 +734,11 @@ it run faster:</p>
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is available from a previous instruction.</li>
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<li>Atomic operations now get legalized into simpler atomic operations if not
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natively supported, easing the implementation burden on targets.</li>
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<li>The bottom-up pre-allocation scheduler is now register pressure aware,
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allowing it to avoid overscheduling in high pressure situations while still
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aggressively scheduling when registers are available.</li>
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<li>A new instruction-level-parallelism pre-allocation scheduler is available,
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which is also register pressure aware. This scheduler has shown substantial
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wins on X86-64 and is on by default.</li>
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<li>We have added two new bottom-up pre-allocation register pressure aware schedulers:
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<ol>
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<li>The hybrid scheduler schedules aggressively to minimize schedule length when registers are available and avoid overscheduling in high pressure situations.</li>
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<li>The instruction-level-parallelism scheduler schedules for maximum ILP when registers are available and avoid overscheduling in high pressure situations.</li>
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</ol></li>
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<li>The tblgen type inference algorithm was rewritten to be more consistent and
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diagnose more target bugs. If you have an out-of-tree backend, you may
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find that it finds bugs in your target description. This support also
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