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fix comments to match code; NFC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232385 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2015-03-16 15:38:48 +00:00
parent b3b90bd679
commit b8434f1cf5
1 changed files with 3 additions and 3 deletions
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6
lib/Target/X86/X86ISelLowering.cpp
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@ -10472,17 +10472,17 @@ SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
// If the vector is wider than 128 bits, extract the 128-bit subvector, insert // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
// into that, and then insert the subvector back into the result. // into that, and then insert the subvector back into the result.
if (VT.is256BitVector() || VT.is512BitVector()) { if (VT.is256BitVector() || VT.is512BitVector()) {
// Get the desired 128-bit vector half. // Get the desired 128-bit vector chunk.
SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
// Insert the element into the desired half. // Insert the element into the desired chunk.
unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits(); unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128; unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
DAG.getConstant(IdxIn128, MVT::i32)); DAG.getConstant(IdxIn128, MVT::i32));
// Insert the changed part back to the 256-bit vector // Insert the changed part back into the bigger vector
return Insert128BitVector(N0, V, IdxVal, DAG, dl); return Insert128BitVector(N0, V, IdxVal, DAG, dl);
} }
assert(VT.is128BitVector() && "Only 128-bit vector types should be left!"); assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");