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PR1260:

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Add final support to get the QT example to compile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35290 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2007-03-23 22:35:46 +00:00
parent e177e307fc
commit b8440a0c39
2 changed files with 27 additions and 7 deletions
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26
include/llvm/IntrinsicsX86.td
View File

@ -581,6 +581,9 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_mmx_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw">, def int_x86_mmx_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>; llvm_v4i16_ty], [IntrNoMem]>;
def int_x86_mmx_pmull_w : GCCBuiltin<"__builtin_ia32_pmullw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>;
def int_x86_mmx_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd">, def int_x86_mmx_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd">,
Intrinsic<[llvm_v2i32_ty, llvm_v4i16_ty, Intrinsic<[llvm_v2i32_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>; llvm_v4i16_ty], [IntrNoMem]>;
@ -590,10 +593,10 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Shift left logical // Shift left logical
def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">, def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">,
Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v2i32_ty], [IntrNoMem]>; llvm_v2i32_ty], [IntrNoMem]>;
def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">, def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v2i32_ty], [IntrNoMem]>; llvm_v2i32_ty], [IntrNoMem]>;
def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">, def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
@ -610,9 +613,22 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
llvm_v2i32_ty], [IntrNoMem]>; llvm_v2i32_ty], [IntrNoMem]>;
def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">, def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">,
Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty,
llvm_v2i32_ty], [IntrNoMem]>;
def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v2i32_ty], [IntrNoMem]>; llvm_v2i32_ty], [IntrNoMem]>;
def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v2i32_ty], [IntrNoMem]>;
}
// Pack ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_mmx_packsswb : GCCBuiltin<"__builtin_ia32_packsswb">,
Intrinsic<[llvm_v8i8_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>;
def int_x86_mmx_packssdw : GCCBuiltin<"__builtin_ia32_packssdw">,
Intrinsic<[llvm_v4i16_ty, llvm_v2i32_ty,
llvm_v2i32_ty], [IntrNoMem]>;
def int_x86_mmx_packuswb : GCCBuiltin<"__builtin_ia32_packuswb">,
Intrinsic<[llvm_v8i8_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>;
} }

8
lib/Target/X86/X86InstrMMX.td
View File

@ -23,7 +23,7 @@
class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
: I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>; : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
: Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>; : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
@ -151,7 +151,6 @@ defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>; defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>; defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
// MMX_PSHUF*, MMX_SHUFP* etc. imm. // MMX_PSHUF*, MMX_SHUFP* etc. imm.
def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{ def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
@ -246,6 +245,11 @@ defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
int_x86_mmx_psra_d>; int_x86_mmx_psra_d>;
// Pack instructions
defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
// Move Instructions // Move Instructions
def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}", []>; "movd {$src, $dst|$dst, $src}", []>;