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Add instruction encodings / disassembly support for l2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -157,6 +157,16 @@ static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -366,7 +376,7 @@ DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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static DecodeStatus
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DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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// Try and decode as a L3R instruction.
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// Try and decode as a L3R / L2RUS instruction.
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unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
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fieldFromInstruction(Insn, 27, 5) << 4;
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switch (Opcode) {
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@ -406,6 +416,15 @@ DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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case 0x11c:
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Inst.setOpcode(XCore::ST8_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x12c:
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Inst.setOpcode(XCore::ASHR_l2rus);
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return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
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case 0x13c:
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Inst.setOpcode(XCore::LDAWF_l2rus);
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return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x14c:
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Inst.setOpcode(XCore::LDAWB_l2rus);
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return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x15c:
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Inst.setOpcode(XCore::CRC_l3r);
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return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
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@ -515,6 +534,34 @@ DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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Inst.addOperand(MCOperand::CreateImm(Op3));
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}
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return S;
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}
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static DecodeStatus
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DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeBitpOperand(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -68,8 +68,21 @@ class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr,
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let DecoderMethod = "Decode2RUSBitpInstruction";
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}
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class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FL2RUS<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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let Inst{31-27} = opc{8-4};
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let Inst{26-20} = 0b1111110;
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let Inst{19-16} = opc{3-0};
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let Inst{15-11} = 0b11111;
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let DecoderMethod = "DecodeL2RUSInstruction";
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}
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// L2RUS with bitp operand
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class _FL2RUSBitp<bits<9> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _FL2RUS<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeL2RUSBitpInstruction";
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}
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class _FRU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -237,25 +237,25 @@ class F3R_np<bits<5> opc, string OpcStr> :
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// Three operand long
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/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
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multiclass FL3R_L2RUS<bits<9> opc, string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
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SDNode OpNode> {
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def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _l2rus : _FL2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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}
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/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
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multiclass FL3R_L2RBITP<bits<9> opc, string OpcStr, SDNode OpNode> {
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def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
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SDNode OpNode> {
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def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _l2rus : _FL2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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}
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class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
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@ -430,10 +430,9 @@ def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
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(ldawf GRRegs:$addr, GRRegs:$offset))]>;
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let neverHasSideEffects = 1 in
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def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
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(ins GRRegs:$addr, i32imm:$offset),
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"ldaw $dst, $addr[$offset]",
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[]>;
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def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, i32imm:$offset),
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"ldaw $dst, $addr[$offset]", []>;
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def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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@ -442,10 +441,9 @@ def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
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(ldawb GRRegs:$addr, GRRegs:$offset))]>;
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let neverHasSideEffects = 1 in
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def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
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(ins GRRegs:$addr, i32imm:$offset),
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"ldaw $dst, $addr[-$offset]",
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[]>;
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def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, i32imm:$offset),
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"ldaw $dst, $addr[-$offset]", []>;
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def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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@ -468,7 +466,7 @@ def REMS_l3r : FL3R<0b110001100, "rems", srem>;
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def REMU_l3r : FL3R<0b110011100, "remu", urem>;
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}
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def XOR_l3r : FL3R<0b000011100, "xor", xor>;
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defm ASHR : FL3R_L2RBITP<0b000101100, "ashr", sra>;
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defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
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let Constraints = "$src1 = $dst" in
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def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
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@ -301,3 +301,14 @@
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# CHECK: xor r4, r3, r9
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0xcd 0xfc 0xec 0x0f
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# l2rus instructions
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# CHECK: ashr r5, r1, 3
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0x57 0xf8 0xec 0x97
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# CHECK: ldaw r11, r10[6]
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0x7a 0xfc 0xec 0x9f
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# CHECK: ldaw r8, r2[-9]
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0x09 0xfd 0xec 0xa7
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