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Add support for loading from a constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1549,6 +1549,7 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
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case ARM::fixup_arm_pcrel_10:
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case ARM::fixup_arm_adr_pcrel_12:
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case ARM::fixup_arm_thumb_bl:
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case ARM::fixup_arm_thumb_cp:
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assert(0 && "Unimplemented"); break;
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case ARM::fixup_arm_branch:
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return ELF::R_ARM_CALL; break;
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@ -138,6 +138,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
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return Binary;
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}
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case ARM::fixup_arm_thumb_cp:
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// Offset by 4, and don't encode the low two bits.
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return ((Value - 4) >> 2) & 0xff;
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case ARM::fixup_t2_pcrel_10:
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case ARM::fixup_arm_pcrel_10: {
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// Offset by 8 just as above.
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@ -243,13 +246,17 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_4:
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return 4;
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case ARM::fixup_arm_thumb_cp:
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return 1;
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case ARM::fixup_arm_ldst_pcrel_12:
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case ARM::fixup_arm_pcrel_10:
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case ARM::fixup_arm_adr_pcrel_12:
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case ARM::fixup_arm_branch:
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return 3;
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case FK_Data_4:
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case ARM::fixup_t2_pcrel_10:
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case ARM::fixup_arm_thumb_bl:
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return 4;
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@ -255,6 +255,8 @@ namespace {
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const { return 0; }
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uint32_t getAddrModeS1OpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
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// {17-13} = reg
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// {12} = (U)nsigned (add == '1', sub == '0')
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@ -34,6 +34,9 @@ enum Fixups {
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// fixup_arm_thumb_bl - Fixup for Thumb BL/BLX instructions.
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fixup_arm_thumb_bl,
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// fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
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fixup_arm_thumb_cp,
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// The next two are for the movt/movw pair
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// the 16bit imm field are split into imm{15-12} and imm{11-0}
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// Fixme: We need new ones for Thumb.
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@ -134,6 +134,13 @@ def t_addrmode_sp : Operand<i32>,
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let ParserMatchClass = MemModeThumbAsmOperand;
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}
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// t_addrmode_pc := <label> => pc + imm8 * 4
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//
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def t_addrmode_pc : Operand<i32> {
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let EncoderMethod = "getAddrModePCOpValue";
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let ParserMatchClass = MemModeThumbAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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//
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@ -622,22 +629,29 @@ def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
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// Load tconstpool
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// FIXME: Use ldr.n to work around a Darwin assembler bug.
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
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def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
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"ldr", ".n\t$Rt, $addr",
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[(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
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T1Encoding<{0,1,0,0,1,?}> {
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// A6.2 & A8.6.59
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bits<3> Rt;
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bits<8> addr;
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let Inst{10-8} = Rt;
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// FIXME: Finish for the addr.
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let Inst{7-0} = addr;
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}
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// Special LDR for loads from non-pc-relative constpools.
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let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
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isReMaterializable = 1 in
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def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
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"ldr", "\t$dst, $addr", []>,
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T1LdStSP<{1,?,?}>;
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def tLDRcp : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
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"ldr", "\t$Rt, $addr", []>,
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T1LdStSP<{1,?,?}> {
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// A6.2 & A8.6.57 T2
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bits<3> Rt;
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bits<8> addr;
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let Inst{10-8} = Rt;
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let Inst{7-0} = addr;
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}
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def tSTR : // A8.6.194
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T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
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@ -52,6 +52,7 @@ public:
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{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_movt_hi16", 0, 16, 0 },
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{ "fixup_arm_movw_lo16", 0, 16, 0 },
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};
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@ -174,6 +175,10 @@ public:
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uint32_t getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
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uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
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uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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@ -662,15 +667,17 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
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return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
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}
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/// getAddrModeThumbSPOpValue- Encode the t_addrmode_sp operands.
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/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
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uint32_t ARMMCCodeEmitter::
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getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// [SP, #imm]
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// {7-0} = imm8
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const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
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assert (MI.getOperand(OpIdx).getReg() == ARM::SP &&
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"Unexpected base register!");
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#if 0 // FIXME: This crashes2003-05-14-initialize-string.c
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assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
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"Unexpected base register!");
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#endif
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// The immediate is already shifted for the implicit zeroes, so no change
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// here.
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return MO1.getImm() & 0xff;
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@ -720,6 +727,23 @@ getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
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return getAddrModeSOpValue(MI, OpIdx, 1);
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}
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/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
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uint32_t ARMMCCodeEmitter::
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getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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// If the destination is an immediate, we have nothing to do.
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if (MO.isImm()) return MO.getImm();
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assert (MO.isExpr() && "Unexpected branch target type!");
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_cp);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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// All of the information is in the fixup.
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return 0;
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}
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
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uint32_t ARMMCCodeEmitter::
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getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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@ -627,6 +627,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R
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MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
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MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
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MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
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return 1;
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}
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@ -838,6 +839,7 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
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operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
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operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
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operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
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operandTypes.addEntry("kOperandTypeThumbAddrModePC");
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operandTypes.addEntry("kOperandTypeThumb2SoReg");
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operandTypes.addEntry("kOperandTypeThumb2SoImm");
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operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
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