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Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.
TableGen has been taught to generate the lists from instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57722 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,6 +19,8 @@
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namespace llvm {
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class TargetRegisterClass;
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//===----------------------------------------------------------------------===//
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// Machine Operand Flags and Description
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//===----------------------------------------------------------------------===//
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@ -107,16 +109,17 @@ namespace TID {
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/// points to this struct directly to describe itself.
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class TargetInstrDesc {
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public:
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unsigned short Opcode; // The opcode number.
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unsigned short Opcode; // The opcode number
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unsigned short NumOperands; // Num of args (may be more if variable_ops)
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unsigned short NumDefs; // Num of args that are definitions.
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unsigned short NumDefs; // Num of args that are definitions
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unsigned short SchedClass; // enum identifying instr sched class
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const char * Name; // Name of the instruction record in td file.
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unsigned Flags; // flags identifying machine instr class
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const char * Name; // Name of the instruction record in td file
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unsigned Flags; // Flags identifying machine instr class
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unsigned TSFlags; // Target Specific Flag values
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const unsigned *ImplicitUses; // Registers implicitly read by this instr
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands.
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const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
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const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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@ -202,6 +205,17 @@ public:
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return ImplicitDefs;
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}
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/// getRegClassBarriers - Return a list of register classes that are
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/// completely clobbered by this machine instruction. For example, on X86
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/// the call instructions will completely clobber all the registers in the
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/// fp stack and XMM classes.
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///
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/// This method returns null if the instruction doesn't completely clobber
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/// any register class.
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const TargetRegisterClass **getRegClassBarriers() const {
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return RCBarriers;
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}
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/// getSchedClass - Return the scheduling class for this instruction. The
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/// scheduling class is an index into the InstrItineraryData table. This
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/// returns zero if there is no known scheduling information for the
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@ -27,6 +27,14 @@ static void PrintDefList(const std::vector<Record*> &Uses,
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OS << "0 };\n";
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}
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static void PrintBarriers(std::vector<Record*> &Barriers,
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unsigned Num, std::ostream &OS) {
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OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
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for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
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OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
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OS << "NULL };\n";
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}
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary Information.
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//===----------------------------------------------------------------------===//
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@ -137,6 +145,33 @@ void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
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}
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}
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void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
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const std::vector<CodeGenRegisterClass> &RCs,
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std::vector<Record*> &Barriers) {
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std::set<Record*> DefSet;
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unsigned NumDefs = Defs.size();
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for (unsigned i = 0; i < NumDefs; ++i)
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DefSet.insert(Defs[i]);
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RCs[i];
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unsigned NumRegs = RC.Elements.size();
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if (NumRegs > NumDefs)
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continue; // Can't possibly clobber this RC.
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bool Clobber = true;
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for (unsigned j = 0; j < NumRegs; ++j) {
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Record *Reg = RC.Elements[j];
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if (!DefSet.count(Reg)) {
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Clobber = false;
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break;
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}
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}
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if (Clobber)
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Barriers.push_back(RC.TheDef);
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}
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}
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//===----------------------------------------------------------------------===//
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// Main Output.
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//===----------------------------------------------------------------------===//
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@ -151,10 +186,14 @@ void InstrInfoEmitter::run(std::ostream &OS) {
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CodeGenTarget &Target = CDP.getTargetInfo();
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const std::string &TargetName = Target.getName();
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Record *InstrInfo = Target.getInstructionSet();
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const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
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// Keep track of all of the def lists we have emitted already.
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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unsigned ListNumber = 0;
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std::map<std::vector<Record*>, unsigned> EmittedBarriers;
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unsigned BarrierNumber = 0;
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std::map<Record*, unsigned> BarriersMap;
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// Emit all of the instruction's implicit uses and defs.
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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@ -167,6 +206,14 @@ void InstrInfoEmitter::run(std::ostream &OS) {
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}
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std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
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if (!Defs.empty()) {
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std::vector<Record*> RCBarriers;
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DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
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if (!RCBarriers.empty()) {
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unsigned &IB = EmittedBarriers[RCBarriers];
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if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
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BarriersMap.insert(std::make_pair(Inst, IB));
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}
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unsigned &IL = EmittedLists[Defs];
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if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
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}
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@ -186,7 +233,7 @@ void InstrInfoEmitter::run(std::ostream &OS) {
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
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emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
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OperandInfoIDs, OS);
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BarriersMap, OperandInfoIDs, OS);
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OS << "};\n";
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OS << "} // End llvm namespace \n";
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}
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@ -194,6 +241,7 @@ void InstrInfoEmitter::run(std::ostream &OS) {
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void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EmittedLists,
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std::map<Record*, unsigned> &BarriersMap,
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const OperandInfoMapTy &OpInfo,
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std::ostream &OS) {
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int MinOperands = 0;
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@ -257,6 +305,12 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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else
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OS << "ImplicitList" << EmittedLists[DefList] << ", ";
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std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
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if (BI == BarriersMap.end())
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OS << "NULL, ";
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else
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OS << "Barriers" << BI->second << ", ";
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// Emit the operand info.
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std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
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if (OperandInfo.empty())
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@ -44,6 +44,7 @@ private:
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EL,
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std::map<Record*, unsigned> &BM,
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const OperandInfoMapTy &OpInfo,
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std::ostream &OS);
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void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
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@ -56,6 +57,10 @@ private:
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// Operand information.
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void EmitOperandInfo(std::ostream &OS, OperandInfoMapTy &OperandInfoIDs);
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std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
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void DetectRegisterClassBarriers(std::vector<Record*> &Defs,
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const std::vector<CodeGenRegisterClass> &RCs,
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std::vector<Record*> &Barriers);
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};
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} // End llvm namespace
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