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bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -555,10 +555,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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CallOpc = (isDirect || Subtarget->hasV5TOps())
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? ARMISD::CALL : ARMISD::CALL_NOLINK;
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}
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if (CallOpc == ARMISD::CALL_NOLINK) {
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// On CALL_NOLINK we must move PC to LR
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if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
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// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
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Chain = DAG.getCopyToReg(Chain, ARM::LR,
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DAG.getRegister(ARM::PC, MVT::i32), InFlag);
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DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
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InFlag = Chain.getValue(1);
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}
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@ -370,6 +370,8 @@ class AI3<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
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class AI4<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
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class AIx2<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
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class AI1x2<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
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@ -546,9 +548,9 @@ let isCall = 1, noResults = 1,
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[(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
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let Uses = [LR] in {
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// ARMv4T
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def BX : AI<(ops GPR:$dst, variable_ops),
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"bx $dst",
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[(ARMcall_nolink GPR:$dst)]>;
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def BX : AIx2<(ops GPR:$dst, variable_ops),
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"mov lr, pc\n\tbx $dst",
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[(ARMcall_nolink GPR:$dst)]>;
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}
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}
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@ -189,12 +189,10 @@ let isCall = 1, noResults = 1,
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def tBLXr : TI<(ops GPR:$dst, variable_ops),
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"blx $dst",
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[(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
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let Uses = [LR] in {
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// ARMv4T
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def tBX : TI<(ops GPR:$dst, variable_ops),
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"bx $dst",
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// ARMv4T
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def tBX : TIx2<(ops GPR:$dst, variable_ops),
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"cpy lr, pc\n\tbx $dst",
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[(ARMcall_nolink GPR:$dst)]>;
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}
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}
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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