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bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lauro Ramos Venancio 2007-03-27 16:19:21 +00:00
parent dd43321079
commit b8a93a45f8
3 changed files with 11 additions and 11 deletions
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6
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -555,10 +555,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
CallOpc = (isDirect || Subtarget->hasV5TOps())
? ARMISD::CALL : ARMISD::CALL_NOLINK;
}
if (CallOpc == ARMISD::CALL_NOLINK) {
// On CALL_NOLINK we must move PC to LR
if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
Chain = DAG.getCopyToReg(Chain, ARM::LR,
DAG.getRegister(ARM::PC, MVT::i32), InFlag);
DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
InFlag = Chain.getValue(1);
}

8
lib/Target/ARM/ARMInstrInfo.td
View File

@ -370,6 +370,8 @@ class AI3<dag ops, string asm, list<dag> pattern>
: I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
class AI4<dag ops, string asm, list<dag> pattern>
: I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
class AIx2<dag ops, string asm, list<dag> pattern>
: I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
class AI1x2<dag ops, string asm, list<dag> pattern>
: I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
@ -546,9 +548,9 @@ let isCall = 1, noResults = 1,
[(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
let Uses = [LR] in {
// ARMv4T
def BX : AI<(ops GPR:$dst, variable_ops),
"bx $dst",
[(ARMcall_nolink GPR:$dst)]>;
def BX : AIx2<(ops GPR:$dst, variable_ops),
"mov lr, pc\n\tbx $dst",
[(ARMcall_nolink GPR:$dst)]>;
}
}

8
lib/Target/ARM/ARMInstrThumb.td
View File

@ -189,12 +189,10 @@ let isCall = 1, noResults = 1,
def tBLXr : TI<(ops GPR:$dst, variable_ops),
"blx $dst",
[(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
let Uses = [LR] in {
// ARMv4T
def tBX : TI<(ops GPR:$dst, variable_ops),
"bx $dst",
// ARMv4T
def tBX : TIx2<(ops GPR:$dst, variable_ops),
"cpy lr, pc\n\tbx $dst",
[(ARMcall_nolink GPR:$dst)]>;
}
}
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {