From b8cab9227a0f6ffbdaae33e3c64268e265008a6a Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Tue, 14 Oct 2008 20:25:08 +0000 Subject: [PATCH] Fix command-line option printing to print two spaces where needed, instead of requiring all "short description" strings to begin with two spaces. This makes these strings less mysterious, and it fixes some cases where short description strings mistakenly did not begin with two spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocBigBlock.cpp | 2 +- lib/CodeGen/RegAllocLinearScan.cpp | 2 +- lib/CodeGen/RegAllocLocal.cpp | 2 +- lib/CodeGen/RegAllocPBQP.cpp | 2 +- lib/CodeGen/RegAllocSimple.cpp | 2 +- lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 2 +- lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 2 +- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 4 ++-- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- lib/CodeGen/VirtRegMap.cpp | 4 ++-- lib/Support/CommandLine.cpp | 2 +- lib/Target/ARM/ARMTargetMachine.cpp | 4 ++-- lib/Target/Alpha/AlphaTargetMachine.cpp | 2 +- lib/Target/CBackend/CBackend.cpp | 2 +- lib/Target/CellSPU/SPUTargetMachine.cpp | 2 +- lib/Target/CppBackend/CPPBackend.cpp | 2 +- lib/Target/IA64/IA64TargetMachine.cpp | 2 +- lib/Target/MSIL/MSILWriter.cpp | 2 +- lib/Target/Mips/MipsTargetMachine.cpp | 4 ++-- lib/Target/PIC16/PIC16TargetMachine.cpp | 2 +- lib/Target/PowerPC/PPCTargetMachine.cpp | 4 ++-- lib/Target/Sparc/SparcTargetMachine.cpp | 2 +- lib/Target/TargetMachine.cpp | 18 +++++++++--------- lib/Target/X86/X86Subtarget.cpp | 4 ++-- lib/Target/X86/X86TargetMachine.cpp | 4 ++-- tools/llc/llc.cpp | 6 +++--- 26 files changed, 43 insertions(+), 43 deletions(-) diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index 0bc95389e36..68c7936e3b9 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -53,7 +53,7 @@ STATISTIC(NumLoads , "Number of loads added"); STATISTIC(NumFolded, "Number of loads/stores folded into instructions"); static RegisterRegAlloc - bigBlockRegAlloc("bigblock", " Big-block register allocator", + bigBlockRegAlloc("bigblock", "Big-block register allocator", createBigBlockRegisterAllocator); namespace { diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 31e47f96b4c..ede387e7b79 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -50,7 +50,7 @@ NewHeuristic("new-spilling-heuristic", cl::init(false), cl::Hidden); static RegisterRegAlloc -linearscanRegAlloc("linearscan", " linear scan register allocator", +linearscanRegAlloc("linearscan", "linear scan register allocator", createLinearScanRegisterAllocator); namespace { diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index 479245224ea..b7df9dd318d 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -37,7 +37,7 @@ STATISTIC(NumStores, "Number of stores added"); STATISTIC(NumLoads , "Number of loads added"); static RegisterRegAlloc - localRegAlloc("local", " local register allocator", + localRegAlloc("local", "local register allocator", createLocalRegisterAllocator); namespace { diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index 107d277f4de..1aea7e2c205 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -60,7 +60,7 @@ using namespace llvm; static RegisterRegAlloc -registerPBQPRepAlloc("pbqp", " PBQP register allocator", +registerPBQPRepAlloc("pbqp", "PBQP register allocator", createPBQPRegisterAllocator); diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index da729ae8dfc..7dc98904abc 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -35,7 +35,7 @@ STATISTIC(NumLoads , "Number of loads added"); namespace { static RegisterRegAlloc - simpleRegAlloc("simple", " simple register allocator", + simpleRegAlloc("simple", "simple register allocator", createSimpleRegisterAllocator); class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass { diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index ef7e143274b..83f7b7364ee 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -31,7 +31,7 @@ STATISTIC(NumDups, "Number of duplicated nodes"); STATISTIC(NumCCCopies, "Number of cross class copies"); static RegisterScheduler - fastDAGScheduler("fast", " Fast suboptimal list scheduling", + fastDAGScheduler("fast", "Fast suboptimal list scheduling", createFastDAGScheduler); namespace { diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index 4b09b7c2631..067407b1eb8 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -37,7 +37,7 @@ STATISTIC(NumNoops , "Number of noops inserted"); STATISTIC(NumStalls, "Number of pipeline stalls"); static RegisterScheduler - tdListDAGScheduler("list-td", " Top-down list scheduler", + tdListDAGScheduler("list-td", "Top-down list scheduler", createTDListDAGScheduler); namespace { diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 2e22b659e41..c605292695b 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -41,11 +41,11 @@ STATISTIC(NumCCCopies, "Number of cross class copies"); static RegisterScheduler burrListDAGScheduler("list-burr", - " Bottom-up register reduction list scheduling", + "Bottom-up register reduction list scheduling", createBURRListDAGScheduler); static RegisterScheduler tdrListrDAGScheduler("list-tdrr", - " Top-down register reduction list scheduling", + "Top-down register reduction list scheduling", createTDRRListDAGScheduler); namespace { diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index dce46ab414b..6e9b2885a8f 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -119,7 +119,7 @@ ISHeuristic("pre-RA-sched", " allocation):")); static RegisterScheduler -defaultListDAGScheduler("default", " Best scheduler for the target", +defaultListDAGScheduler("default", "Best scheduler for the target", createDefaultScheduler); namespace llvm { diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 26d019b2841..1c3c13931b5 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -56,8 +56,8 @@ static cl::opt SpillerOpt("spiller", cl::desc("Spiller to use: (default: local)"), cl::Prefix, - cl::values(clEnumVal(simple, " simple spiller"), - clEnumVal(local, " local spiller"), + cl::values(clEnumVal(simple, "simple spiller"), + clEnumVal(local, "local spiller"), clEnumValEnd), cl::init(local)); diff --git a/lib/Support/CommandLine.cpp b/lib/Support/CommandLine.cpp index 571b0338677..498131390c3 100644 --- a/lib/Support/CommandLine.cpp +++ b/lib/Support/CommandLine.cpp @@ -953,7 +953,7 @@ void generic_parser_base::printOptionInfo(const Option &O, for (unsigned i = 0, e = getNumOptions(); i != e; ++i) { size_t NumSpaces = GlobalWidth-strlen(getOption(i))-8; cout << " =" << getOption(i) << std::string(NumSpaces, ' ') - << " - " << getDescription(i) << "\n"; + << " - " << getDescription(i) << "\n"; } } else { if (O.HelpStr[0]) diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 29a9d848663..a96e25f22e7 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -29,8 +29,8 @@ static cl::opt DisableIfConversion("disable-arm-if-conversion",cl::Hidden, cl::desc("Disable if-conversion pass")); // Register the target. -static RegisterTarget X("arm", " ARM"); -static RegisterTarget Y("thumb", " Thumb"); +static RegisterTarget X("arm", "ARM"); +static RegisterTarget Y("thumb", "Thumb"); // No assembler printer by default ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0; diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index 15c6948e494..54bfc05d126 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -22,7 +22,7 @@ using namespace llvm; // Register the targets -static RegisterTarget X("alpha", " Alpha (incomplete)"); +static RegisterTarget X("alpha", "Alpha (incomplete)"); const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const { return new AlphaTargetAsmInfo(*this); diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index 9a797480844..7ec649d0c52 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -49,7 +49,7 @@ using namespace llvm; // Register the target. -static RegisterTarget X("c", " C backend"); +static RegisterTarget X("c", "C backend"); namespace { /// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index f0512f3b151..b8dd5aa8cfe 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -24,7 +24,7 @@ using namespace llvm; namespace { // Register the targets RegisterTarget - CELLSPU("cellspu", " STI CBEA Cell SPU"); + CELLSPU("cellspu", "STI CBEA Cell SPU"); } const std::pair * diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index fb836638e5f..95c4ad7dc50 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -72,7 +72,7 @@ static cl::opt NameToGenerate("cppfor", cl::Optional, cl::init("!bad!")); // Register the target. -static RegisterTarget X("cpp", " C++ backend"); +static RegisterTarget X("cpp", "C++ backend"); namespace { typedef std::vector TypeList; diff --git a/lib/Target/IA64/IA64TargetMachine.cpp b/lib/Target/IA64/IA64TargetMachine.cpp index c789a8649a2..1b811b645d7 100644 --- a/lib/Target/IA64/IA64TargetMachine.cpp +++ b/lib/Target/IA64/IA64TargetMachine.cpp @@ -26,7 +26,7 @@ using namespace llvm; extern "C" int IA64TargetMachineModule; int IA64TargetMachineModule = 0; -static RegisterTarget X("ia64", " IA-64 (Itanium)"); +static RegisterTarget X("ia64", "IA-64 (Itanium)"); const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const { return new IA64TargetAsmInfo(*this); diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp index 8e4ca1fcd97..a27c0cc688a 100644 --- a/lib/Target/MSIL/MSILWriter.cpp +++ b/lib/Target/MSIL/MSILWriter.cpp @@ -45,7 +45,7 @@ namespace { } -static RegisterTarget X("msil", " MSIL backend"); +static RegisterTarget X("msil", "MSIL backend"); bool MSILModule::runOnModule(Module &M) { ModulePtr = &M; diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 276868cbb20..25a0eaa857c 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -20,8 +20,8 @@ using namespace llvm; // Register the target. -static RegisterTarget X("mips", " Mips"); -static RegisterTarget Y("mipsel", " Mipsel"); +static RegisterTarget X("mips", "Mips"); +static RegisterTarget Y("mipsel", "Mipsel"); const TargetAsmInfo *MipsTargetMachine:: createTargetAsmInfo() const diff --git a/lib/Target/PIC16/PIC16TargetMachine.cpp b/lib/Target/PIC16/PIC16TargetMachine.cpp index 26b573a0122..df164697224 100644 --- a/lib/Target/PIC16/PIC16TargetMachine.cpp +++ b/lib/Target/PIC16/PIC16TargetMachine.cpp @@ -23,7 +23,7 @@ using namespace llvm; namespace { // Register the targets - RegisterTarget X("pic16", " PIC16 14-bit"); + RegisterTarget X("pic16", "PIC16 14-bit"); } PIC16TargetMachine:: diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 3d737515db2..22b459cb748 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -23,9 +23,9 @@ using namespace llvm; // Register the targets static RegisterTarget -X("ppc32", " PowerPC 32"); +X("ppc32", "PowerPC 32"); static RegisterTarget -Y("ppc64", " PowerPC 64"); +Y("ppc64", "PowerPC 64"); // No assembler printer by default PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0; diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index cc730f82671..80af77e6808 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -19,7 +19,7 @@ using namespace llvm; // Register the target. -static RegisterTarget X("sparc", " SPARC"); +static RegisterTarget X("sparc", "SPARC"); const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const { // FIXME: Handle Solaris subtarget someday :) diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp index c05efd041ea..a1d6fa7eb97 100644 --- a/lib/Target/TargetMachine.cpp +++ b/lib/Target/TargetMachine.cpp @@ -102,13 +102,13 @@ DefRelocationModel( cl::init(Reloc::Default), cl::values( clEnumValN(Reloc::Default, "default", - " Target default relocation model"), + "Target default relocation model"), clEnumValN(Reloc::Static, "static", - " Non-relocatable code"), + "Non-relocatable code"), clEnumValN(Reloc::PIC_, "pic", - " Fully relocatable, position independent code"), + "Fully relocatable, position independent code"), clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", - " Relocatable external references, non-relocatable code"), + "Relocatable external references, non-relocatable code"), clEnumValEnd)); static cl::opt DefCodeModel( @@ -118,15 +118,15 @@ DefCodeModel( cl::init(CodeModel::Default), cl::values( clEnumValN(CodeModel::Default, "default", - " Target default code model"), + "Target default code model"), clEnumValN(CodeModel::Small, "small", - " Small code model"), + "Small code model"), clEnumValN(CodeModel::Kernel, "kernel", - " Kernel code model"), + "Kernel code model"), clEnumValN(CodeModel::Medium, "medium", - " Medium code model"), + "Medium code model"), clEnumValN(CodeModel::Large, "large", - " Large code model"), + "Large code model"), clEnumValEnd)); static cl::opt diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index 0d90ef61169..871e7af83f1 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -23,8 +23,8 @@ static cl::opt AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset), cl::desc("Choose style of code to emit from X86 backend:"), cl::values( - clEnumValN(X86Subtarget::ATT, "att", " Emit AT&T-style assembly"), - clEnumValN(X86Subtarget::Intel, "intel", " Emit Intel-style assembly"), + clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"), + clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"), clEnumValEnd)); diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 860868adf16..923823b98cd 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -32,9 +32,9 @@ int X86TargetMachineModule = 0; // Register the target. static RegisterTarget -X("x86", " 32-bit X86: Pentium-Pro and above"); +X("x86", "32-bit X86: Pentium-Pro and above"); static RegisterTarget -Y("x86-64", " 64-bit X86: EM64T and AMD64"); +Y("x86-64", "64-bit X86: EM64T and AMD64"); // No assembler printer by default X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0; diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp index 03972b10ca7..f185490725a 100644 --- a/tools/llc/llc.cpp +++ b/tools/llc/llc.cpp @@ -80,11 +80,11 @@ FileType("filetype", cl::init(TargetMachine::AssemblyFile), cl::desc("Choose a file type (not all types are supported by all targets):"), cl::values( clEnumValN(TargetMachine::AssemblyFile, "asm", - " Emit an assembly ('.s') file"), + "Emit an assembly ('.s') file"), clEnumValN(TargetMachine::ObjectFile, "obj", - " Emit a native object ('.o') file [experimental]"), + "Emit a native object ('.o') file [experimental]"), clEnumValN(TargetMachine::DynamicLibrary, "dynlib", - " Emit a native dynamic library ('.so') file" + "Emit a native dynamic library ('.so') file" " [experimental]"), clEnumValEnd));