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[DAGCombiner] Canonicalize vector constants for ADD/MUL/AND/OR/XOR re-association
Scalar integers are commuted to move constants to the RHS for re-association - this ensures vectors do the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234092 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
4d1e15c54f
commit
b8d7733666
@ -1598,7 +1598,8 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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if (N0C && N1C)
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return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
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// canonicalize constant to RHS
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if (N0C && !N1C)
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if (isConstantIntBuildVectorOrConstantInt(N0) &&
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!isConstantIntBuildVectorOrConstantInt(N1))
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return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
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// fold (add x, 0) -> x
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if (N1C && N1C->isNullValue())
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@ -1995,8 +1996,9 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
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if (N0IsConst && N1IsConst)
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return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
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// canonicalize constant to RHS
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if (N0IsConst && !N1IsConst)
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// canonicalize constant to RHS (vector doesn't have to splat)
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if (isConstantIntBuildVectorOrConstantInt(N0) &&
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!isConstantIntBuildVectorOrConstantInt(N1))
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return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
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// fold (mul x, 0) -> 0
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if (N1IsConst && ConstValue1 == 0)
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@ -2829,7 +2831,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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if (N0C && N1C)
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return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
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// canonicalize constant to RHS
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if (N0C && !N1C)
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if (isConstantIntBuildVectorOrConstantInt(N0) &&
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!isConstantIntBuildVectorOrConstantInt(N1))
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return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
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// fold (and x, -1) -> x
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if (N1C && N1C->isAllOnesValue())
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@ -3545,7 +3548,8 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
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if (N0C && N1C)
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return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
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// canonicalize constant to RHS
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if (N0C && !N1C)
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if (isConstantIntBuildVectorOrConstantInt(N0) &&
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!isConstantIntBuildVectorOrConstantInt(N1))
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return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
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// fold (or x, 0) -> x
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if (N1C && N1C->isNullValue())
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@ -3887,7 +3891,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
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if (N0C && N1C)
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return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
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// canonicalize constant to RHS
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if (N0C && !N1C)
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if (isConstantIntBuildVectorOrConstantInt(N0) &&
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!isConstantIntBuildVectorOrConstantInt(N1))
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return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
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// fold (xor x, 0) -> x
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if (N1C && N1C->isNullValue())
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@ -11,11 +11,22 @@ define <4 x i32> @add_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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ret <4 x i32> %3
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}
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define <4 x i32> @add_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @add_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: paddd %xmm1, %xmm0
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;CHECK-NEXT: retq
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%1 = add <4 x i32> <i32 1, i32 -2, i32 3, i32 -4>, %a0
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%2 = add <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, %a1
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%3 = add <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @mul_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: pmulld %xmm1, %xmm0
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;CHECK-NEXT: pmulld .LCPI1_0(%rip), %xmm0
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;CHECK-NEXT: pmulld .LCPI2_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
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%2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>
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@ -23,11 +34,23 @@ define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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ret <4 x i32> %3
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}
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define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @mul_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: pmulld %xmm1, %xmm0
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;CHECK-NEXT: pmulld .LCPI3_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0
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%2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1
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%3 = mul <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @and_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: andps %xmm1, %xmm0
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;CHECK-NEXT: andps .LCPI2_0(%rip), %xmm0
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;CHECK-NEXT: andps .LCPI4_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
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%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
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@ -35,11 +58,23 @@ define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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ret <4 x i32> %3
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}
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define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @and_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: andps %xmm1, %xmm0
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;CHECK-NEXT: andps .LCPI5_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
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%2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
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%3 = and <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @or_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: orps %xmm1, %xmm0
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;CHECK-NEXT: orps .LCPI3_0(%rip), %xmm0
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;CHECK-NEXT: orps .LCPI6_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
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%2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
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@ -47,14 +82,38 @@ define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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ret <4 x i32> %3
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}
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define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @or_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: orps %xmm1, %xmm0
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;CHECK-NEXT: orps .LCPI7_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
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%2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
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%3 = or <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @xor_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: xorps %xmm1, %xmm0
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;CHECK-NEXT: xorps .LCPI4_0(%rip), %xmm0
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;CHECK-NEXT: xorps .LCPI8_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
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%2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
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%3 = xor <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @xor_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: xorps %xmm1, %xmm0
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;CHECK-NEXT: xorps .LCPI9_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
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%2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
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%3 = xor <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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