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Fix 80-column violations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-01-03 23:19:12 +00:00
parent ac1ed44d95
commit b90d2a9046
1 changed files with 5 additions and 4 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
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@ -7438,8 +7438,8 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
} }
/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
/// take a 2 x i32 value to shift plus a shift amount. /// and take a 2 x i32 value to shift plus a shift amount.
SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
assert(Op.getNumOperands() == 3 && "Not a double-shift!"); assert(Op.getNumOperands() == 3 && "Not a double-shift!");
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -13958,7 +13958,8 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
// Bitcast the loaded value to a vector of the original element type, in // Bitcast the loaded value to a vector of the original element type, in
// the size of the target vector type. // the size of the target vector type.
SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector); SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
ScalarInVector);
unsigned SizeRatio = RegSz/MemSz; unsigned SizeRatio = RegSz/MemSz;
// Redistribute the loaded elements into the different locations. // Redistribute the loaded elements into the different locations.