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Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147495 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7438,9 +7438,9 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
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/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
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/// take a 2 x i32 value to shift plus a shift amount.
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/// and take a 2 x i32 value to shift plus a shift amount.
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SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
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SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
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assert(Op.getNumOperands() == 3 && "Not a double-shift!");
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assert(Op.getNumOperands() == 3 && "Not a double-shift!");
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EVT VT = Op.getValueType();
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EVT VT = Op.getValueType();
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unsigned VTBits = VT.getSizeInBits();
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unsigned VTBits = VT.getSizeInBits();
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@ -13958,7 +13958,8 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
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// Bitcast the loaded value to a vector of the original element type, in
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// Bitcast the loaded value to a vector of the original element type, in
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// the size of the target vector type.
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// the size of the target vector type.
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SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector);
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SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
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ScalarInVector);
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unsigned SizeRatio = RegSz/MemSz;
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unsigned SizeRatio = RegSz/MemSz;
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// Redistribute the loaded elements into the different locations.
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// Redistribute the loaded elements into the different locations.
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