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[mips] Add more Octeon cnMips instructions
Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kai Nacke
parent
6408bdcacd
commit
b96fc4a5ea
@ -234,29 +234,45 @@ let Predicates = [HasCnMips] in {
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class Count1s<string opstr, RegisterOperand RO>:
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InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
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[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr>;
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[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
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let TwoOperandAliasConstraint = "$rd = $rs";
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}
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class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
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InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
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!strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
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[(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
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NoItinerary, FrmR, opstr> {
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let TwoOperandAliasConstraint = "$rt = $rs";
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}
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class SetCC64_R<string opstr, PatFrag cond_op> :
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InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
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!strconcat(opstr, "\t$rd, $rs, $rt"),
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[(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
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II_SEQ_SNE, FrmR, opstr>;
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II_SEQ_SNE, FrmR, opstr> {
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let TwoOperandAliasConstraint = "$rd = $rs";
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}
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// Unsigned Byte Add
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def BADDu : InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
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"baddu\t$rd, $rs, $rt",
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[(set GPR64Opnd:$rd, (and (add GPR64Opnd:$rs,
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GPR64Opnd:$rt), 255))],
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II_BADDU, FrmR, "baddu">, ADD_FM<0x1c, 0x28> {
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let isCommutable = 1;
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let isReMaterializable = 1;
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}
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let Pattern = [(set GPR64Opnd:$rd,
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(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
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def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
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ADD_FM<0x1c, 0x28>;
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// Multiply Doubleword to GPR
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let Defs = [HI0, LO0, P0, P1, P2] in
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def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
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ADD_FM<0x1c, 0x03>;
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// Extract a signed bit field /+32
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def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
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def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
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// Clear and insert a bit field /+32
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def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
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def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
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// Move to multiplier/product register
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def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
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def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
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@ -275,6 +291,7 @@ def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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@ -489,6 +489,22 @@ class WAIT_FM : StdArch {
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let Inst{5-0} = 0x20;
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}
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class EXTS_FM<bits<6> funct> : StdArch {
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bits<5> rt;
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bits<5> rs;
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bits<5> pos;
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bits<5> lenm1;
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bits<32> Inst;
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let Inst{31-26} = 0x1c;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = lenm1;
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let Inst{10-6} = pos;
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let Inst{5-0} = funct;
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}
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class MTMR_FM<bits<6> funct> : StdArch {
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bits<5> rs;
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@ -1,6 +1,20 @@
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; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=OCTEON
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; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=MIPS64
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define i64 @addi64(i64 %a, i64 %b) nounwind {
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entry:
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; OCTEON-LABEL: addi64:
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; OCTEON: jr $ra
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; OCTEON: baddu $2, $4, $5
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; MIPS64-LABEL: addi64:
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; MIPS64: daddu
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; MIPS64: jr
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; MIPS64: andi
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%add = add i64 %a, %b
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%and = and i64 %add, 255
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ret i64 %and
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}
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define i64 @mul(i64 %a, i64 %b) nounwind {
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entry:
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; OCTEON-LABEL: mul:
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@ -2,11 +2,22 @@
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# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28]
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# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28]
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# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03]
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# CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28]
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# CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2]
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# CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72]
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# CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3]
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# CHECK: cins32 $22, $22, 9, 22 # encoding: [0x72,0xd6,0xb2,0x73]
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# CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03]
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# CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03]
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# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03]
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# CHECK: dmul $21, $21, $25 # encoding: [0x72,0xb9,0xa8,0x03]
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# CHECK: dpop $9, $6 # encoding: [0x70,0xc0,0x48,0x2d]
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# CHECK: dpop $15, $22 # encoding: [0x72,0xc0,0x78,0x2d]
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# CHECK: dpop $12, $12 # encoding: [0x71,0x80,0x60,0x2d]
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# CHECK: exts $4, $25, 27, 15 # encoding: [0x73,0x24,0x7e,0xfa]
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# CHECK: exts $15, $15, 17, 6 # encoding: [0x71,0xef,0x34,0x7a]
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# CHECK: exts32 $4, $13, 10, 8 # encoding: [0x71,0xa4,0x42,0xbb]
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# CHECK: exts32 $15, $15, 11, 20 # encoding: [0x71,0xef,0xa2,0xfb]
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# CHECK: mtm0 $15 # encoding: [0x71,0xe0,0x00,0x08]
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# CHECK: mtm1 $16 # encoding: [0x72,0x00,0x00,0x0c]
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# CHECK: mtm2 $17 # encoding: [0x72,0x20,0x00,0x0d]
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@ -15,16 +26,30 @@
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# CHECK: mtp2 $20 # encoding: [0x72,0x80,0x00,0x0b]
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# CHECK: pop $9, $6 # encoding: [0x70,0xc0,0x48,0x2c]
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# CHECK: pop $8, $19 # encoding: [0x72,0x60,0x40,0x2c]
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# CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c]
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# CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a]
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# CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a]
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# CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b]
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# CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b]
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baddu $9, $6, $7
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baddu $17, $18, $19
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dmul $9, $6
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baddu $2, $3
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cins $25, $10, 22, 2
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cins $9, 17, 29
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cins32 $15, $2, 18, 8
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cins32 $22, 9, 22
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dmul $9, $6, $7
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dmul $19, $24, $25
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dmul $9, $6
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dmul $21, $25
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dpop $9, $6
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dpop $15, $22
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dpop $12
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exts $4, $25, 27, 15
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exts $15, 17, 6
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exts32 $4, $13, 10, 8
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exts32 $15, 11, 20
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mtm0 $15
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mtm1 $16
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mtm2 $17
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@ -33,5 +58,8 @@
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mtp2 $20
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pop $9, $6
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pop $8, $19
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pop $2
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seq $25, $23, $24
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seq $6, $24
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sne $25, $23, $24
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sne $23, $20
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