diff --git a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index cf33782365b..1a1b58bd26e 100644
--- a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2062,6 +2062,10 @@ SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
   SmallVector<SDValue, 2> Ops;
   Ops.push_back(In);
 
+  // C11 leaves it implementation-defined whether these operations trigger an
+  // inexact exception. IEEE says they don't.  Unfortunately, Darwin decided
+  // they do so we sometimes have to insert a special instruction just to set
+  // the right bit in FPSR.
   if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) {
     SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In);
     Ops.push_back(SDValue(FRINTX, 1));